Capturing Video in Raw Data Mode

3.11 Capturing Video in Raw Data Mode

In order to capture video in the raw data mode, the following steps are needed:

1)Set VCxSTOP1 to specify size of an image to be captured (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits of the captured image size in pixels).

2)Write to VCxTHRLD to set the capture threshold. Every time the number of received pixels reaches the number specified by the VCTHRLD1 bits, a YEVTx is generated by the video capture module.

3)Configure a DMA channel to move data from YSRCx to a destination in the DSP memory. The channel transfers should be triggered by the YEVTx. The size of the transfers should be set to VCTHRLD1/4 for 8-bit mode, VCTHRLD1/3 for dense 10-bit mode, VCTHRLD1/2 for 10-bit or 16-bit mode, or VCTHRLD1 for 20-bit mode. The DMA must start on a doubleword boundary and move an even number of words.

4)Write to the video port interrupt enable register (VPIE) to enable overrun (COVRx) and capture complete (CCMPx) interrupts, if desired.

5)Write to VCxCTL to:

-Set capture mode (CMODE = x1x for raw data mode).

-Choose capture operation (CON, FRAME bits).

-Set 10-bit pack mode (10BPK bits), if 10-bit operation is selected.

-Enable raw data sync (RDS), if desired.

-Set VCEN bit to enable capture.

6)Capture starts when the ICAPEN signal is asserted and VCEN = 1. Data is captured on every VCLKINx rising edge when CAPENx is active. DMA events (YEVTx) are generated as triggered by VCxTHRLD1. When a complete data block has been captured (DCOUNT = VCYSTOP and VCXSTOP combined value), the FRMC bit in VCxSTAT is set causing the CCMPx bit in VPIS to be set. This generates a DSP interrupt, if CCMPx is enabled in VPIE.

7)If continuous capture is enabled, the video port begins capturing again on the next VCLKIN rising edge when CAPEN is valid. If noncontinuous capture is enabled, the next data block is captured during which the DSP must clear the FRMC bit or further capture is disabled. If single frame capture is enabled, capture is disabled until the DSP clears the FRMC bit (at which point, raw data sync must again be performed if enabled).

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Video Capture Port

SPRU629

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Texas Instruments TMS320C64x DSP manual Capturing Video in Raw Data Mode

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.