Y/C Video Capture Mode

The 10-bit Y/C mode uses three FIFOs for color separation. Two samples are packed into each word with zero or sign extension as shown in Figure 3–6.

Figure 3–6. 10-Bit Y/C FIFO Packing

Y FIFO

Cb FIFO

Cr FIFO

Y FIFO

Cb FIFO

Cr FIFO

 

 

VCLKINA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDIN[9–0]

Y 0

Y 1

Y 2

 

 

Y 3

Y 4

Y 5

Y 6

 

 

Y 7

Y 8

Y 9

Y 10

Y 11

 

 

 

 

VDIN[19–10]

Cb 0

Cr 0

Cb 1

 

 

Cr 1

Cb 2

Cr 2

Cb 3

 

 

Cr 3

Cb 4

Cr 4

Cb 5

Cr 5

 

 

63

58 57

 

48 47

42 41

 

32 31

26 25

 

16 15

10

9

 

0

 

 

0 / SE

 

Y 15

 

 

 

0 / SE

 

 

 

Y 14

 

 

 

0 / SE

 

 

 

Y 13

 

 

 

0 / SE

 

 

Y 12

 

 

0 / SE

 

Y 11

 

 

 

0 / SE

 

 

 

Y 10

 

 

 

0 / SE

 

 

 

Y 9

 

 

 

0 / SE

 

 

Y 8

 

 

0 / SE

 

Y 7

 

 

 

0 / SE

 

 

 

Y 6

 

 

 

0 / SE

 

 

 

Y 4

 

 

 

0 / SE

 

 

Y 4

 

 

0 / SE

 

Y 3

 

 

 

 

 

 

 

Y 2

 

 

 

0 / SE

 

 

 

Y 1

 

 

 

0 / SE

 

 

Y 0

63

58 57

 

48 47

42 41

 

32 31

26 25

 

16 15

10

9

 

0

 

 

0 / SE

 

Cb 7

 

 

 

0 / SE

 

 

 

Cb 6

 

 

 

0 / SE

 

 

 

Cb 5

 

 

 

0 / SE

 

 

Cb 4

 

 

0 / SE

 

Cb 3

 

 

 

0 / SE

 

 

 

Cb 2

 

 

 

0 / SE

 

 

 

Cb 1

 

 

 

0 / SE

 

 

Cb 0

63

58 57

 

48 47

42 41

 

32 31

26 25

 

16 15

10

9

 

0

 

 

0 / SE

 

Cr 7

 

 

 

0 / SE

 

 

 

Cr 6

 

 

 

0 / SE

 

 

 

Cr 5

 

 

 

0 / SE

 

 

Cr 4

 

 

0 / SE

 

Cr 3

 

 

 

0 / SE

 

 

 

Cr 2

 

 

 

0 / SE

 

 

 

Cr 1

 

 

 

0 / SE

 

 

Cr 0

 

 

 

 

 

 

 

 

 

 

 

 

 

Little-Endian Packing

 

 

 

 

 

 

 

 

 

 

63

58 57

 

48 47

42 41

 

32 31

26 25

 

16 15

10

9

 

0

 

 

0 / SE

 

 

Y 12

 

 

 

0 / SE

 

 

 

Y 13

 

 

 

0 / SE

 

 

 

Y 14

 

 

0 / SE

 

 

Y 15

 

 

0 / SE

 

 

Y 8

 

 

 

0 / SE

 

 

 

Y 9

 

 

 

0 / SE

 

 

 

Y 10

 

 

0 / SE

 

 

Y 11

 

 

0 / SE

 

 

Y 4

 

 

 

0 / SE

 

 

 

Y 4

 

 

 

0 / SE

 

 

 

Y 6

 

 

0 / SE

 

 

Y 7

 

 

0 / SE

 

 

Y 0

 

 

 

0 / SE

 

 

 

Y 1

 

 

 

0 / SE

 

 

 

Y 2

 

 

0 / SE

 

 

Y 3

 

63

58 57

 

48 47

42 41

 

32 31

26 25

 

16 15

10

9

 

0

 

 

0 / SE

 

 

Cb 4

 

 

 

0 / SE

 

 

 

Cb 5

 

 

 

0 / SE

 

 

 

Cb 6

 

 

0 / SE

 

 

Cb 7

 

 

0 / SE

 

 

Cb 0

 

 

 

0 / SE

 

 

 

Cb 1

 

 

 

0 / SE

 

 

 

Cb 2

 

 

0 / SE

 

 

Cb 3

 

63

58 57

 

48 47

42 41

 

32 31

26 25

 

16 15

10

9

 

0

 

 

0 / SE

 

 

Cr 4

 

 

 

0 / SE

 

 

 

Cr 5

 

 

 

0 / SE

 

 

 

Cr 6

 

 

0 / SE

 

 

Cr 7

 

 

0 / SE

 

 

Cr 0

 

 

 

0 / SE

 

 

 

Cr 1

 

 

 

0 / SE

 

 

 

Cr 2

 

 

0 / SE

 

 

Cr 3

 

Big-Endian Packing

SPRU629

Video Capture Port

3-15

Page 76 Page 78
Page 77
Image 77
Texas Instruments TMS320C64x DSP manual VDIN9-0 VDIN19-10 Little-Endian Packing Big-Endian Packing
Page 76 Page 78

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
Top Page Image Contents