BT.656 and Y/C Mode Field and Frame Operation

3.4 BT.656 and Y/C Mode Field and Frame Operation

Because DMAs are used to transfer data from the capture FIFOs to memory, there is a large amount of flexibility in the way that capture fields and frames are transferred and stored in memory. In some cases, for example a DMA structure can be created to provide a set of ping-pong or round-robin memory buffers to which a continuous stream of fields are stored without DSP interven- tion. In other cases, the DSP may need to modify DMA pointer addresses after each field or frame is captured. In some applications, only one field may be captured and the other ignored completely, or a frame may need to be ignored in order to have time to process a previous frame. The video port addresses these issues by providing programmable control over different aspects of the capture process.

3.4.1Capture Determination and Notification

The video port treats the capture of every field as a separate operation. In order to accommodate various capture scenarios, DMA structures, and processing flows, the video port employs a flexible capture and DSP notification method. This is programmed using the CON, FRAME, CF1, and CF2 bits in VCxCTL.

The CON bit controls the capture of multiple fields or frames. When CON = 1, continuous capture is enabled, the video port captures incoming fields (assuming the VCEN bit is set) without the need for DSP interaction. It relies on a DMA structure with circular buffering capability to service the capture FIFOs. When CON = 0, continuous capture is disabled, the video port sets a field or frame capture complete bit (F1C, F2C, or FRMC) in VCxSTAT upon the capture of each field as determined by the state of the other capture control bits (FRAME, CF1, and CF2). Once the capture complete bit is set, at most, one more field or frame can be received before capture operation is halted. This prevents subsequent data from overwriting previous fields until the DSP has a chance to update DMA pointers or process those fields. When a capture halt occurs, the video port stops capturing data (for the halted field). It then checks the appropriate capture complete bit at the start of each subsequent field and resumes capture if the bit has been cleared.

The CON, FRAME, CF1, and CF2 bits encode the capture operations as listed in Table 3–6.

SPRU629

Video Capture Port

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Texas Instruments TMS320C64x DSP BT.656 and Y/C Mode Field and Frame Operation, Capture Determination and Notification
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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