Texas Instruments TMS320C64x DSP specs

Video Display Registers

Table 4–13. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Field Descriptions

				Description
Bit	field†	symval†	Value	BT.656 and Y/C Mode	Raw Data Mode
31–28	Reserved	–	0	Reserved. The reserved bit location is always read as
				0. A value written to this field has no effect.

27–16	VBLNKYSTOP2	OF(value)	0–FFFh	Specifies the line (in	Specifies the line (in
				FLCOUNT) where	FLCOUNT) where vertical
				VBLNK inactive edge	blanking ends (VBLNK
				occurs for field 2. Does	inactive edge) for field 2.
				not affect EAV/SAV V bit
				operation.

15–12	Reserved	–	0	Reserved. The reserved bit location is always read as
				0. A value written to this field has no effect.

11–0	VBLNKXSTOP2	OF(value)	0–FFFh	Specifies the pixel (in	Specifies the pixel (in
				FPCOUNT) where	FPCOUNT) where
				VBLNK inactive edge	vertical blanking ends
				occurs for field 2.	(VBLNK inactive edge)
					for field 2.

† For CSL implementation, use the notation VP_VDVBLKE2_field_symval

4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1)

The video display field 1 image offset register (VDIMGOFF1) defines the field 1 image offset and specifies the starting location of the displayed image relative to the start of the active display. The VDIMGOFF1 is shown in Figure 4–47 and described in Table 4–14.

The image line counter (ILCOUNT) is reset to 1 on the first image line (when FLCOUNT = VBLNKYSTOP1 + IMGVOFF1). If the NV bit is set, ILCOUNT is reset to 1 when FLCOUNT = VBLNKYSTOP1 – IMGVOFF1. Display image pixels are output in field 1 beginning on the line where ILCOUNT = 1. The default output values or blanking values are output during active lines prior to ILCOUNT = 1. For a negative offset, IMGVOFF1 must not be greater than VBLNKYSTOP1. The field 1 active image must not overlap the field 2 active image.

The image pixel counter (IPCOUNT) is reset to 0 at the start of an active line image. Once ILCOUNT = 1, image pixels from the FIFO are output on each line in field 1 beginning when FPCOUNT = IMGHOFF1. If the NH bit is set, IPCOUNT is reset when FPCOUNT = FRMWIDTH – IMGHOFF1. The default output values or blanking values are output during active pixels prior to IMGHOFF1.

4-68

Video Display Port

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual Video Display Field 1 Image Offset Register VDIMGOFF1

Models: TMS320C64x DSP

Bit

field†

Value

VBLNKYSTOP2

OF(value)

VBLNKXSTOP2

OF(value)

4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1)

TMS320C64x DSP specifications