Video Port Functionality Subsets / Video Port Throughput and Latency

2.5.2FIFO Size

Some low-cost device implementations with narrow video ports width or restricted to lower video frequency operations may use a reduced FIFO size. FIFO size does not affect the DMA request mechanism. The selection of 8-bit or 10-bit port width automatically cuts the FIFO size in half with support for only a single channel of operation.

2.6 Video Port Throughput and Latency

Because of the large amount of buffering provided within the video port and the programmable threshold used to generate DMA events, the required DMA latency is difficult to calculate. Because video data is real time, the video port’s external interface may not be stalled so module throughput must be maintained.

2.6.1Video Capture Throughput

In order to maintain throughput during video capture operation, the capture FIFO must be emptied at a faster rate than it is filled. The time to completely fill the capture FIFO may be represented by the formula tF + n(tH), where tF is the time to fill the FIFO with active samples, tH is the horizontal blanking time, and n is the number of lines of active video that the FIFO can hold. Maximum throughput requirements for capture occur during HDTV resolution Y/C mode. The BT.1120 standard (1125 line/60 Hz mode) specifies a line size of 2200 Y samples (1920 active) and 1100 ea. Cb and Cr samples (960-ea. active) at a sample rate of 74.25 MHz. This means that the horizontal blanking time is 280/74.25 MHz or 3.77 ∝ s. In Y/C mode, the Y buffer is 2560 bytes and the Cr/Cb buffers are 1280 bytes each. The number of samples that the buffers can hold depends on the buffer packing mode as listed in Table 2–2.

SPRU629

Video Port

2-13

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Texas Instruments TMS320C64x DSP manual Video Port Throughput and Latency, Fifo Size, Video Capture Throughput
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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