SPRU629

Display Timing Examples

The interlaced BT.656 vertical output timing is shown in Figure 4–34. The BT.656 active field 1 is 244-lines high and active field 2 is 243-lines high. This example shows the 480-line image window centered in the screen. This results in an IMGVOFFn of 3 lines and also results in a nondata line at the end of field 1 due to its extra active line.

The VBLNK and VSYNC signals are shown as they would be output for active- low operation. Note that only one of the two signals is actually available exter- nally. The VBLNK and VSYNC edges for field 1 occur at the end of an active line so their XSTART/XSTOP values are set to 720 (start of blanking). For field 2, VBLNK and VSYNC edges occur during the middle of the active horizontal line so their XSTART/XSTOP values are set to 360. Note that, from an analog standpoint, vertical blanking begins a half-line before digital blanking so that VBLNKYSTART2 is set to 263 (with VBLNKXSTART2 set to 360) while VBITSET2 is programmed to 264. For true BT.656 operation, neither VBLNK nor VSYNC would be used.

The FLD output is setup to transition at the start of each analog field (start of vertical blanking). Since EAV[F] transitions on lines 4 and 266, this requires programming FBITCLR to 4, FBITSET to 266, FLD1YSTART to 1, and FLD2YSTART to 263. Note that FLD2XSTRT is 360 so that the field indicator output changes halfway through the line.

The ILCOUNT operation follows the description in section 4.1.2. ILCOUNT resets to 1 at the first displayed line (FLCOUNT = VBLNKSTOPx + IMGVOFFx) and stops counting at the last displayed pixel (IPCOUNT = IMGVSIZEx). The operation during nondisplay time is not a requirement, it could continue count- ing until the next FLCOUNT = VBLNKSTOPx + IMGVOFFx point or it could reset immediately after IMGVSIZEx or when FLCOUNT is reset.

The active horizontal output column shows the output data during the active portion of the horizontal line. It is assumed that the DVEN bit in VDCTL is set to enable the default output.

Video Display Port

4-37

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual SPRU629

Models: TMS320C64x DSP

SPRU629

TMS320C64x DSP specifications