BT.656 and Y/C Mode Field and Frame Operation

 

Table 3–6. BT.656 and Y/C Mode Capture Operation (Continued)

 

 

 

 

 

 

 

VCxCTL Bit

 

 

 

 

 

 

 

 

 

CON

FRAME

CF2

CF1

Operation

 

 

 

 

 

 

 

1

0

1

0

Continuous field 2 capture. Capture only field 2. F2C is set after field 2

 

 

 

 

 

capture and causes CCMPx to be set (CCMPx interrupt can be

 

 

 

 

 

disabled). The video port continues capturing field 2 fields, regardless

 

 

 

 

 

of the state of F2C.

 

1

0

1

1

Reserved

 

1

1

0

0

Continuous frame capture. Capture both fields. FRMC is set after

 

 

 

 

 

field 2 capture and causes CCMPx to be set (CCMPx interrupt can be

 

 

 

 

 

disabled). The video port continues capturing frames, regardless of the

 

 

 

 

 

state of FRMC.

 

1

1

0

1

Continuous progressive frame capture. Capture field 1. FRMC is set

 

 

 

 

 

after field 1 capture and causes CCMPx to be set (CCMPx interrupt can

 

 

 

 

 

be disabled). The video port continues capturing frames, regardless of

 

 

 

 

 

the state of FRMC. (Functions identically to continuous field 1 capture

 

 

 

 

 

mode except the FRMC bit is used instead of the F1C bit.)

 

1

1

1

0

Reserved

 

1

1

1

1

Reserved

 

 

 

 

 

 

 

3.4.2Vertical Synchronization

The video port uses a capture window to determine which incoming data samples to capture in each field. The capture module uses a vertical line counter (VCOUNT) to track which video line is currently being received. The line count- er is compared to the appropriate capture window start (VCYSTART1 or VCYSTART2) and stop (VCYSTOP1 or VCYSTOP2) values for the current field to determine if the current line is within the capture window. In order to correctly align the capture window within the field, the capture module must know which line should correspond to the first line of the field, that is, when to reset the line counter. This point may vary depending on the type of capture being performed and the signals available for vertical synchronization. The video port allows the vertical counter reset trigger to be determined by programming the EXC and VRST bits in VCxCTL. The encoding of these bits is shown in Table 3–7. Note that VModes 2 and 3 are only available for single channel operation (channel A).

SPRU629

Video Capture Port

3-19

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Texas Instruments TMS320C64x DSP manual Vertical Synchronization, VCxCTL Bit
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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