Video Port Registers | Texas Instruments TMS320C64x DSP guide

Video Port FIFO / Video Port Registers

For Y/C video display, the FIFO is configured as a single channel split into sep- arate Y, Cb, and Cr buffers with separate read pointers and write registers (YDSTA, CBDST, and CRDST). Figure 1–10 shows how Y data is output on the VDOUT[9–0] half of the bus and Cb/Cr data is multiplexed and output on the VDOUT[19–10] half of the bus.

Figure 1–10. Y/C Video Display FIFO Configuration

Display FIFO

YDSTA

CBDST

CRDST

			VDOUT[9–0]
64			8/10
			8/10
	Y Buffer
	(2560 bytes)
64	Cb Buffer
	Cb Buffer
	(1280 bytes)		VDOUT[19–10]
		8/10	VDOUT[19–10]
		8/10
64	Cr Buffer	8/10
	Cr Buffer	8/10
	(1280 bytes)

1.3 Video Port Registers

The video port configuration register space is divided into several different sections with registers grouped by function including top-level video port control, video capture control, video display control, and GPIO.

The registers for controlling the video port are in section 2.7.

The registers for controlling the video capture mode of operation are shown in section 3.13. An additional space is dedicated for FIFO read pseudo-registers as shown in section 3.14. This space requires high-speed access and is not mapped to the register access bus.

The registers for controlling the video display mode of operation are shown in section 4.12. An additional space is dedicated for FIFO write pseudo-registers as shown in section 4.14. This space requires high-speed access and is not mapped to the register access bus.

The registers for controlling the general-purpose input/output (GPIO) are shown in section 5.1.

1-12

Overview

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

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For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP Video Port Registers, 10. Y/C Video Display Fifo Configuration

Models: TMS320C64x DSP

Figure 1–10. Y/C Video Display FIFO Configuration

YDSTA

1.3 Video Port Registers

TMS320C64x DSP specifications