Y/C Video Capture Mode

3.3.3Y/C Image Window and Capture

The SDTV Y/C format (CCIR601) is an interlaced format consisting of two fields just like BT.656. HDTV Y/C formats may be interlaced or progressive scan. For interlaced capture, the capture windows are programmed identically to BT.656 mode. For progressive scan formats, only field1 is used.

In Y/C mode, HCOUNT increments on every luma sample period (every VCLKINA rising edge) for which capture is enabled. Once YCOUNT = VCYSTART, line capture begins when HCOUNT = VCXSTART. It continues until HCOUNT = VCXSTOP. A field’s capture is complete when HCOUNT = VCXSTOP and VCOUNT = VCYSTOP.

For the Y/C video capture mode, the FIFO buffer is divided into three sections (three buffers). One section is 2560 bytes deep and is dedicated for storage of Y data samples. The other two sections are dedicated for storage of Cb and Cr data samples, respectively. The buffers for Cb and Cr samples are each 1280 bytes deep. The incoming video data stream is separated into Y, Cb, and Cr data streams, scaled (if selected) and the Y, Cb, and Cr buffers are filled. Each of the three buffers has a memory-mapped location associated with it; YSRC, CBSRC, and CRSRC. The YSRC, CBSRC, and CRSRC locations are read only and are used by DMAs to access video data samples stored in the FIFOs. Reads must always be 64 bits.

If video capture is enabled, pixels in the capture window are captured in the Y, Cb, and Cr buffers. The video capture module uses the YEVT, CbEVT, and CrEVT events to notify the DMA controller to copy data from the capture buff- ers to the DSP memory. The number of pixels required to generate the events is set by the VCTHRLDn bits in VCxTHRLD (the VCTHRLDn value must be an even number for Y/C mode). The capture module generates the events after VCTHRLDn new pixels have been received. On every YEVT, the DMA should move data from the Y buffer to DSP memory using the YSRC register as the source address. On every CbEVT, the DMA should move data from the Cb buffer to DSP memory using the CBSRC register as the source address. On every CrEVT, the DMA should move data from the Cr buffer to DSP memory using the CRSRC register as the source address. Note that transfer size from the Cb and Cr buffers is half of the transfer size from the Y buffer since for every four Y samples, there are two Cb and two Cr samples.

The three DMA events are generated simultaneously when VCTHRLDn is reached. Each event is reenabled when the first read of the respective FIFO by the requested DMA begins.

SPRU629

Video Capture Port

3-13

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Texas Instruments TMS320C64x DSP manual 3 Y/C Image Window and Capture
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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