BT.656 Video Display Mode

4.2 BT.656 Video Display Mode

The BT.656 display mode outputs 8-bit or 10-bit 4:2:2 co-sited luma and chroma data multiplexed into a single data stream. Pixels are output in pairs with each pair consisting of two luma samples and two chroma samples. The chroma samples are associated with the first luma pixel of the pair. Output pixels are valid on the positive edge of VCLKOUT in the sequence CbYCrY as shown in Figure 4–8.

Figure 4–8. BT.656 Output Sequence

VCLKOUT

VDOUT[9–0]

Cb0

Y0

Cr0

Y1

Cb1

Y2

Cr1

Y3

Cb2

Y4

4.2.1Display Timing Reference Codes

The end active video (EAV) code and start active video (SAV) code are issued at the start of each video line. EAV and SAV codes have a fixed format. The format is shown in Table 3–2 (page 3-4).The EAV and SAV codes define the end and start of the horizontal-blanking interval, respectively, and they also indicate the current field number and the vertical blanking interval. The SAV and EAV codes have a 4-bit protection field to ensure valid codes. The video display module generates these protection bits as part of the SAV and EAV codes. Table 3–3 (page 3-5)shows possible combinations of valid SAV and EAV codes with their protection bits. The video display pipeline generates SAV and EAV sync codes and inserts them into the output video stream according to the BT.656 specification.

The BT.656 line timing is shown in Figure 4–9 and Figure 4–10. Each line begins with an EAV code, a blanking interval, an SAV code, followed by the line of active video. The EAV code indicates the end of active video for the previous line, and the SAV code indicates the start of active video for the current line.

Figure 4–9. 525/60 BT.656 Horizontal Blanking Timing

FPCOUNT

VCLKOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

One Line

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

720

721

722

723

 

855

856

857

 

 

0

 

1

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

426841440

Next Line

718

719

720

721

722

723

 

 

 

 

 

 

Blanking

 

 

 

 

 

 

 

 

 

 

 

Active Video

Cb359

VDOUT[9–0]

FF.C 00.0 00.0

XY.0

80.0

10.0

80.0

10.0

80.0

10.0

FF.C

00.0

00.0

XY.0

Cb0

Y0

Cr0

Y1

Cb1

Y2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y 718

Cr 359

Y 719

FF.C

00.0

00.0

XY.0

80.0

10.0

80.0

10.0

EAV Blanking Data

SAV

EAV

SPRU629

Video Display Port

4-9

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Texas Instruments TMS320C64x DSP manual BT.656 Video Display Mode, Display Timing Reference Codes
Page 153 Page 155

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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