TSI Capture Mode

Figure 3–22. Parallel TSI Capture

VCLKIN

 

 

 

 

CAPEN

 

 

 

 

PACSTRT

 

 

 

 

VDIN[9:2]

Sync Byte Byte 1

Byte 2

Byte 3

Byte 4

Start Capture

3.8.3TSI Capture Error Detection

The video port checks for two types of errors during TSI capture. The first is a packet error on the incoming packet as indicated by an active PACERR signal. If PACERR is active during any of the first eight bytes of a packet and error packet filtering is enabled (ERRFILT bit in TSICTL is set), then the video port will ignore (not capture) the incoming data until the next PACSTRT is received. If error packet filtering is not enabled or if PACERR becomes active sometime after the first eight bytes of the packet, the entire packet is captured and the PERR bit is set in the timestamp inserted at the end of the packet.

The second error detected is an early PACSTRT error. This occurs when an active PACSTRT is detected before an entire packet (as determined by the packet size programmed in VCASTOP) has been captured. The port will con- tinue to capture the expected packet size but will set the PSTERR bit in the timestamp inserted at the end of the packet. After capture completion, the port will wait for a subsequent PACSTRT before beginning capture of another packet.

3.8.4Synchronizing the System Clock

Synchronization is an important aspect of decoding and presenting data in real-time digital data delivery systems. This is addressed in MPEG-2 transport packets by transmitting timing information in the adaptation fields of selected data packets. This value serves as a reference for timing comparison in the receiving system. The program clock reference (PCR) header, shown in Figure 3–23, is a 48-bit field (six bits are reserved). A 42-bit value is transmitted within the 48-bit stream and consists of a 33-bit PCR field that represents a 90-kHz clock sample and a 9-bit PCR extension field that repre- sents a 27-MHz clock sample. The PCR indicates the expected time at the completion of reading the field from the bit stream at the transport decoder. The transport data packets are in-sync with the encoder time clock.

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Video Capture Port

SPRU629

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Texas Instruments TMS320C64x DSP manual TSI Capture Error Detection, Synchronizing the System Clock, Vclkin Capen Pacstrt
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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