Texas Instruments TMS320C64x DSP specification

Video Display Registers

Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)

					Description
Bit	field†	symval†	Value	BT.656 and Y/C Mode		Raw Data Mode
21	HXS			Horizontal external synchronization enable bit.
		OUTPUT	0	VCTL1 is an output.
		HSINPUT	1	VCTL1 is an external horizontal sync input.

20	VCTL3S			VCTL3 output select bit.
		CBLNK	0	Output CBLNK
		FLD	1	Output FLD

19–18	VCTL2S			VCTL2 output select bit.
		VYSYNC	0	Output VSYNC
		VBLNK	1h	Output VBLNK
		CSYNC	2h	Output CSYNC
		FLD	3h	Output FLD

17–16	VCTL1S			VCTL1 output select bit.
		HYSYNC	0	Output HSYNC
		HBLNK	1h	Output HBLNK
		AVID	2h	Output AVID
		FLD	3h	Output FLD

15	VDEN			Video display enable bit. Other bits in VDCTL (except RSTCH and
				BLKDIS bits) may only be changed when VDEN = 0.
		DISABLE	0	Video display is disabled.
		ENABLE	1	Video display is enabled.

14	DPK			10-bit packing format select bit.
		N10UNPK	0	Normal 10-bit unpacking
		D10UNPK	1	Dense 10-bit unpacking

†For CSL implementation, use the notation VP_VDCTL_field_symval

‡ For complete encoding of these bits, see Table 4–4.

SPRU629

Video Display Port

4-57

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual Value BT.656 and Y/C Mode Raw Data Mode

Models: TMS320C64x DSP

Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)

Bit

field†

Value

BT.656 and Y/C Mode

Raw Data Mode

OUTPUT

FLD

VBLNK

FLD

FLD

DISABLE

D10UNPK

Dense 10-bit unpacking

SPRU629

TMS320C64x DSP specifications