BT.656 Video Display Mode

Figure 4–10. 625/50 BT.656 Horizontal Blanking Timing

FPCOUNT

VCLKOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

One Line

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

720

721

722

723

 

861

862

863

 

 

0

 

1

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4280 4 1440

Next Line

718

719

720

721

722

723

Blanking

VDOUT[9–0]

FF.C

00.0

00.0

XY.0

80.0

10.0

80.0

10.0

 

Active Video

80.0 10.0 FF.C 00.0 00.0 XY.0 Cb 0 Y 0 Cr 0 Y 1 Cb 1 Y 2

Cb 359

Y 718

Cr 359

Y 719

FF.C

00.0

00.0

XY.0

80.0

10.0

80.0

10.0

EAV Blanking Data

SAV

EAV

SAV and EAV codes are identified by a 3-byte preamble of FFh, 00h, and 00h. This combination must be avoided in the video data output by the video port to prevent accidental generation of an invalid sync code. The video display module provides programmable maximum and minimum value clipping on the video data to prevent this possibility.

The typical values for H, V, and F on different lines are shown in Table 4–2 and Figure 4–11.

F and V are only allowed to change at EAV sequences. The EAV and SAV sequences must occupy the first four words and the last four words of the digital horizontal-blanking interval, respectively. The EAV code is inserted when FPCOUNT = HBLNKSTART. The SAV code is inserted when

FPCOUNT = HBLNKSTOP.

Table 4–2. BT.656 Frame Timing

Line Number

625/50

525/60

F

V

Description

624–625

1–3

1

1

Vertical blanking for field 1, EAV/SAV code still indicates field 2.

1–22

4–19

0

1

Vertical blanking for field 1. Change EAV/SAV code to field 1.

23–310

20–263

0

0

Active video, field 1.

311–312

264–265

0

1

Vertical blanking for field 2, EAV/SAV code still indicates field 1.

313–335

266–282

1

1

Vertical blanking for field 2. Change EAV/SAV code to field 2.

336–623

283–525

1

0

Active video, field 2.

 

 

 

 

 

4-10

Video Display Port

SPRU629

Page 155
Image 155
Texas Instruments TMS320C64x DSP manual BT.656 Frame Timing, Line Number

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.