Blkdis, Disable Enable, Fxs | Texas Instruments TMS320C64x DSP

Video Display Registers

Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)

				Description
Bit	field†	symval†	Value	BT.656 and Y/C Mode	Raw Data Mode
30	BLKDIS			Block display events bit. BLKDIS functions as a display FIFO reset
				without affecting the current programmable register values.
				The video display module continues to function normally, the
				counters count, control outputs are generated, EAV/SAV codes are
				generated for BT.656 and Y/C modes, and default or blanking data
				is output during active display time. No data is moved to the
				display FIFOs because no events occur. The F1D, F2D, and
				FRMD bits in VDSTAT are still set when fields or frames are
				complete.
		CLEAR	0	Clearing BLKDIS does not enable DMA events during the field in
				which the bit is cleared. DMA events are enabled at the start of the
				next frame after the one in which the bit is cleared. This allows the
				DMA to always be synced to the proper field.
		BLOCK	1	Blocks DMA events and flushes the display FIFOs.

29	Reserved	–	0	Reserved. The reserved bit location is always read as 0. A value
				written to this field has no effect.

28	PVPSYN			Previous video port synchronization enable bit.
		DISABLE	0
		ENABLE	1	Output timing is locked to preceding video port (VP2 is locked to
				VP1 or VP1 is locked to VP0, see Figure 4–7 on page 4-8).

27–24	Reserved	–	0	Reserved. The reserved bit location is always read as 0. A value
				written to this field has no effect.

23	FXS			Field external synchronization enable bit.
		OUTPUT	0	VCTL3 is an output.
		FSINPUT	1	VCTL3 is an external field sync input.

22	VXS			Vertical external synchronization enable bit.
		OUTPUT	0	VCTL2 is an output.
		VSINPUT	1	VCTL2 is an external vertical sync input.

†For CSL implementation, use the notation VP_VDCTL_field_symval

‡ For complete encoding of these bits, see Table 4–4.

4-56

Video Display Port

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

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Texas Instruments TMS320C64x DSP manual Blkdis, Disable Enable, Fxs, Output, Fsinput, Vsinput

Models: TMS320C64x DSP

Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)

Bit

field†

BT.656 and Y/C Mode

BLKDIS

BLOCK

DISABLE

ENABLE

FXS

OUTPUT

FSINPUT

VSINPUT

VCTL2 is an external vertical sync input.

TMS320C64x DSP specifications