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Texas Instruments TMS320C64x DSP manual Vertical Synchronization Programming, VC xCTL Bit VMode

Models: TMS320C64x DSP

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BT.656 and Y/C Mode Field and Frame Operation

Table 3–7. Vertical Synchronization Programming

	VCxCTL Bit
VMode	EXC	VRST	Vertical Counter Reset Point

0	0	0	First EAV with V=1 after EAV with V=0 – beginning of vertical blanking period.
			VCOUNT increments on each EAV.
1	0	1	First EAV with V=0 after EAV with V=1 – first active line. VCOUNT
			increments on each EAV.
2	1	0	On HCOUNT reset after VCTL2 input active edge – beginning of vertical
			blanking or vertical sync period. (VCTL2 must be configured as vertical
			control signal). VCOUNT increments when HCOUNT is reset.
3	1	1	On HCOUNT reset after VCTL2 input inactive edge – end of vertical sync or
			first active scan line. (VCTL2 must be configured as vertical control signal).
			VCOUNT increments when HCOUNT is reset.

VMode 0 is used for BT.656 or Y/C capture (with embedded control) and corre- sponds to most digital video standards that number lines beginning with the start of vertical blanking. VMode 1 can also be used for BT.656 or Y/C capture but counts from the first active video line. This makes field detection more straightforward in some instances (see section 3.4.4) and allows the VCYSTARTn bit to be set to 1, but also has the effect of associating vertical blanking periods with the end of the previous field rather than the beginning of the current field. (This could be an issue when capturing VBI data.) VCOUNT operation for VMode 0 and VMode 1 is shown in Figure 3–8.

VMode 2 and VMode 3 are used for BT.656 or Y/C capture without embedded EAV/SAV codes and allow alignment with either the active or inactive edge of the vertical control signal on VCTL2. This can be a VBLNK or VSYNC signal from the video decoder.

3-20

Video Capture Port

SPRU629

Image 82

Texas Instruments TMS320C64x DSP Vertical Synchronization Programming, VC xCTL Bit VMode, Vertical Counter Reset Point

Contents

Literature Number SPRU629 April Important Notice Read This First Trademarks Contents Discusses operation of the video capture port Video Capture PortVCASTRT2, VCBSTRT2 VCASTRT1, VCBSTRT1VCASTOP1, VCBSTOP1 VCASTOP2, VCBSTOP211.1 VDVSYNE2 General Purpose I/O OperationVcxo Interpolated Control Port Figures Xii Figures Xiii Video Port Tables Xvi Tables Xvii Overview TopicVideo Port SPRU629 Channel a VCLK1 VCLK2 VCTL1 VCTL2VCTL3 Channel BVideo Port Fifo DMA InterfaceVideo Capture Fifo Configurations Ysrca Cbsrca Crsrca Ysrcb Cbsrcb CrsrcbYsrca Y/C Video Capture Fifo Configuration Ysrca Cbsrca CrsrcaVideo Display Fifo Configurations Ydsta Cbdst Crdst10-Bit Raw Video Display Fifo Configuration Ydsta Ydstb10. Y/C Video Display Fifo Configuration Video Port RegistersVideo Capture Signal Mapping Video Port Pin MappingVideo Display Signal Mapping Usage Raw Data Display ModeVdin Bus Usage for Capture Modes Capture Mode BT.656 Raw DataData Bus 10-Bit 16-Bit 20-Bit Mode Vdin Data Bus Usage for Capture ModesVdout Data Bus Usage for Display Modes Vdout Data Bus Usage for Display ModesVideo Port Power-On Reset Reset OperationPeripheral Bus Reset Software Port Reset Capture Channel ResetDisplay Channel Reset Interrupt Operation DMA Operation Capture DMA Event GenerationCapture DMA Event Generation Flow Diagram Fifo ≥Display DMA Event Generation Display DMA Event Generation Flow Diagram DMA Size and Threshold Restrictions DMA Interface Operation Video Port Functional Clocks ClocksVideo Port Functionality Subsets Data Bus WidthFifo Size Video Port Throughput and LatencyVideo Capture Throughput Y/C Video Capture Fifo Capacity Bit Bit Dense 10-BitRaw Video Display Fifo Capacity Video Display ThroughputBit Bit Dense 10/16-Bit 20-Bit Samples 5120 3840 2560 1280 Video Port Control Registers Video Port Control RegistersAcronym Register Name Section Bit Video Port Control Register VpctlVideo Port Control Register Vpctl Field Descriptions Value DescriptionNone Reverse None ClearVCLK2P None ActivelowOperating Mode Video Port Operating Mode SelectionVpctl Bit Video Port Status Register Vpstat Video Port Status Register Vpstat Field DescriptionsVideo Port Interrupt Enable Register Vpie Ccmpb SerrbDcna Lfda Tick STC Video Port Interrupt Status Register VpisDcna Dcmp Lfda Sfda VINTA2 VINTA1 Serra Ccmpa CovraVcount = Ystop Vcbctl Out of the port. The DMA complete interrupt can be used to BT.656 or Y/C capture mode Lfda is set when long field Vcactl Video Capture Port Video Capture Mode Selection Video Capture Mode SelectionTSI Bit Cmode Bits Mode Description BT.656 Video Capture Mode 1 BT.656 Capture Channels2 BT.656 Timing Reference Codes BT.656 Video Timing Reference CodesLine Information Bits Protection Bits Error Correction by Protection BitsBT.656 Protection Bits Received F, V, and H Bits010 011 100 101 3 BT.656 Image Window and CaptureP 0 Bits Video Capture Parameters Common Video Source Parameters4 BT.656 Data Sampling 5 BT.656 Fifo Packing Bit BT.656 Fifo PackingVDIN9-0 / VDIN19-10 Cb Cr 0 Y Cb 1 Y Bit BT.656 Dense Fifo Packing 1 Y/C Capture Channels Y/C Video Capture Mode2 Y/C Timing Reference Codes 3 Y/C Image Window and Capture 4 Y/C Fifo Packing Bit Y/C Fifo PackingVDIN9-0 VDIN19-10 Little-Endian Packing Big-Endian Packing Bit Y/C Dense Fifo Packing BT.656 and Y/C Mode Field and Frame Operation Capture Determination and NotificationVC xCTL Bit BT.656 and Y/C Mode Capture OperationOperation Vertical Synchronization VCxCTL BitVertical Synchronization Programming Vertical Counter Reset PointVC xCTL Bit VMode Vcount Operation Example EXC = Horizontal Synchronization Programming Horizontal Counter Reset PointHorizontal Synchronization VCxCTL Bit HModeHcount Operation Example EXC = Field Detect Method Field IdentificationField Identification Programming EAV code11.Field 1 Detection Timing Short and Long Field DetectInput Filter Modes 10. Input Filter Mode SelectionVideo Input Filtering Filter OperationChrominance Resampling Operation Scaling Operation13 /2 Scaled Co-Sited Filtering SAV Edge Pixel ReplicationEAV 16. Capture Window Not Requiring Edge Pixel Replication Xstart Xsize SAVHorizontal Ancillary Hanc Data Capture Ancillary Data CaptureVertical Ancillary Vanc Data Capture Raw Data Capture Mode Raw Data Capture Notification11. Raw Data Mode Capture Operation Raw Data Fifo Packing17 -Bit Raw Data Fifo Packing 19 -Bit Dense Raw Data Fifo Packing 21 -Bit Raw Data Fifo Packing TSI Capture Features TSI Capture ModeTSI Data Capture Synchronizing the System Clock TSI Capture Error DetectionVclkin Capen Pacstrt PCR CtmodeTSI Data Capture Notification 12. TSI Capture Mode OperationVcactl Bit TSI TSI Fifo Writing to the FifoVclkin PerrCapture Line Boundary Conditions Reading from the FifoIpcount = IMGHSIZE78 Vclkout FifoCapturing Video in BT.656 or Y/C Mode Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Capturing Data in TSI Capture Mode Handling Fifo Overrun Condition in Raw Data ModeHandling Fifo Overrun Condition in TSI Capture Mode Video Capture Registers 13. Video Capture Control RegistersVideo Capture Channel x Status Register VCASTAT, Vcbstat BT.656 or Y/C Mode Raw Data Mode TSI Mode Description BitVcfld Value BT.656 or Y/C Mode Raw Data Mode TSI ModeDetected Video Capture Channel a Control Register Vcactl FIELD1 BlockRdfe FIELD2V1EAV EavfidFDL V0EAVHalf CON ‡Description Raw Data Mode TSI Mode SSE VcystartVCXSTART/VCVBLNKP Vcxstart VcvblnkpVcystop VcxstopField† Symval† FFFh Last captured line Not used VIF1 VIF2 FSCL2VINT2 VINT1VIF2 SPRU629 VCTHRLD2 VCTHRLD1CAPEVTCT2 CAPEVTCT1Vrst Hrst Vcen PK10B Lfde Sfde Resmpl Video Capture Channel B Control Register VcbctlCON Frame CF2 CF1 F1C, F2C, and Frmc status bits, in VCBSTAT, are not EAV or Not used VCTL1 active edge CON‡ Capture field Not usedTSI Capture Control Register Tsictl Enstc Tcken Sten CtmodeValue BT.656, Y/C Mode TSI Mode Or Raw Data Mode 24. TSI Capture Control Register Tsictl Field DescriptionsInpcr BT.656, Y/C Mode TSI Mode Or Raw Data ModeTSI Clock Initialization LSB Register Tsiclkinitl Bit FieldInpcrm TSI Clock Initialization MSB Register TsiclkinitmInpcre TSI System Time Clock LSB Register Tsistclkl 42. TSI System Time Clock LSB Register TsistclklPcre Pcrm TSI System Time Clock MSB Register TsistclkmPcre TSI System Time Clock Compare LSB Register Tsistcmpl ATCTSI System Time Clock Compare MSB Register Tsistcmpm 45. TSI System Time Clock Compare MSB Register TsistcmpmTSI System Time Clock Compare Mask LSB Register Tsistmskl AtcmTSI System Time Clock Compare Mask MSB Register Tsistmskm TSI System Time Clock Ticks Interrupt Register Tsiticks Tickct34. Video Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw DataVideo Capture Fifo Registers 35. Video Capture Fifo Registers FunctionVideo Display Port Dmode Bits Mode Description Video Display Mode SelectionVideo Display Mode Selection Image TimingNtsc Compatible Interlaced Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display CountersHorizontal Blanking and Horizontal Sync Timing FpcountVblnk Sync Signal GenerationFlcount VsyncExternal Sync Operation Port Sync OperationBT.656 Video Display Mode Display Timing Reference CodesBT.656 Frame Timing Line Number11.Digital Vertical F and V Transitions Blanking Codes 3 BT.656 Image Display4 BT.656 Fifo Unpacking 12 -Bit BT.656 Fifo Unpacking13 -Bit BT.656 Fifo Unpacking 14. BT.656 Dense Fifo Unpacking Y/C Video Display Mode 1 Y/C Display Timing Reference Codes3 Y/C Image Display 2 Y/C Blanking Codes4 Y/C Fifo Unpacking 16 -Bit Y/C Fifo Unpacking 17 -Bit Y/C Fifo Unpacking 18 -Bit Y/C Dense Fifo Unpacking Output Filter Modes Output Filter Mode SelectionVideo Output Filtering Vdctl Bit19. Chrominance Resampling 20 x Co-Sited Scaling 23. Luma Edge Replication Horizontal Ancillary Hanc Data Display Raw Data Display ModeAncillary Data Display Vertical Ancillary Vanc Data DisplayRaw Mode RGB Output Support Raw Data Fifo Unpacking26 -Bit Raw Fifo Unpacking 28 -Bit Raw Fifo Unpacking 30 -Bit Raw 3/4 Fifo Unpacking Video Display Field and Frame Operation Display Determination and NotificationDisplay Operation CON Frame DF2 DF1Video Display Event Generation Display Line Boundary Conditions 32. Display Line Boundary Example Display Timing Examples Interlaced BT.656 Timing Example33. BT.656 Interlaced Display Horizontal Timing Example SPRU629 34. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display Example 35. Raw Interlaced Display Horizontal Timing SPRU629 36. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example 37. Y/C Progressive Display Horizontal Timing Example SPRU629 38. Y/C Progressive Display Vertical Timing Example Displaying Video in BT.656 or Y/C Mode Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Displaying Video in Raw Data Mode Handling Underrun Condition of the Display Fifo Video Display Registers Video Display Control RegistersVideo Display Status Register Vdstat Video Display Status Register Vdstat Field Descriptions Video Display Control Register Vdctl BT.656 and Y/C Mode Raw Data ModeVideo Display Control Register Vdctl Field Descriptions FXS Disable EnableBlkdis OutputValue BT.656 and Y/C Mode Raw Data Mode Rgbx BlankingFrmdis FlddisFrmheight Video Display Frame Size Register VdfrmszFrmwidth Video Display Horizontal Blanking Register Vdhblnk HbdlaHblnkstop DelayHblnkstart VBLNKYSTART1 VBLNKXSTART1VBLNKYSTOP1 VBLNKXSTOP1Field† Symval† VBLNKYSTART2 VBLNKXSTART2VBLNKYSTOP2 VBLNKXSTOP2Video Display Field 1 Image Offset Register VDIMGOFF1 IMGHOFF1 IMGVOFF1Negoff IMGVSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGHSIZE1 IMGVOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGHOFF2 None IMGVSIZE2 Video Display Field 2 Image Size Register VDIMGSZ2IMGHSIZE2 FLD1YSTART Video Display Field 1 Timing Register VDFLDT1FLD1XSTART FLD2YSTART Video Display Field 2 Timing Register VDFLDT2FLD2XSTART Video Display Threshold Register Vdthrld IncpixVDTHRLD2 VDTHRLD1Hsyncstop Video Display Horizontal Synchronization Register VdhsyncHsyncstart VSYNCYSTART1 VSYNCXSTART1VSYNCYSTOP1 VSYNCXSTOP1VSYNCYSTART2 VSYNCXSTART2VSYNCYSTOP2 VSYNCXSTOP2Hrld Video Display Counter Reload Register VdreloadVrld CrldDISPEVT2 Video Display Display Event Register VddispevtDISPEVT1 Clipyhigh Clipylow Video Display Clipping Register VdclipClipchigh ClipclowCrdefval Cbdefval Video Display Default Display Value Register VddefvalYdefval Defval CrdefvalVideo Display Vertical Interrupt Register Vdvint 64. Video Display Vertical Interrupt Register VdvintFbitset Video Display Field Bit Register VdfbitFbitclr VBITCLR1 VBITSET1Field† Symval† VBITCLR2 VBITSET2Field† Symval† 34. Video Display Register Recommended Values Video Display Registers Recommended ValuesRegister Field 525/60 Value 625/50 Value Vdfbit Fbitclr Fbitset VDVSYNS2 VSYNCXSTART2VDVSYNE2 VSYNCXSTOP2 VDVBIT1 VBITSET136. Video Display Fifo Registers Function Video Display Fifo Registers35. Video Display Fifo Registers Register BT.656 or Y/C Raw DataGeneral Purpose I/O Operation Gpio RegistersGpio Registers Video Port RegistersClass Revision Video Port Peripheral Identification Register VppidType ClassVideo Port Peripheral Control Register PCR Soft FreeStop PerenSoft CompPFUNC22 Video Port Pin Function Register PfuncVideo Port Pin Function Register Pfunc Field Descriptions NormalVDATA10TO19 PFUNC20PFUNC10 PFUNC0PDIR22 Video Port Pin Direction Register PdirVideo Port Pin Direction Register Pdir Field Descriptions VCTL3INVCTL2OUT PDIR21VCTL2IN PDIR20VDATA8TO9OUT PDIR8VDATA8TO9IN PDIR4PDIN12 Video Port Pin Data Input Register PdinPDIN20 PDIN7 PDIN6Video Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Output Register Pdout PDOUT21 Video Port Pin Data Out Register Pdout Field DescriptionsPDOUT20 Video Port Pin Data Set Register Pdset PDSET21 Video Port Pin Data Set Register Pdset Field DescriptionsPDSET20 Video Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register PdclrVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Interrupt Enable Register Pien Video Port Pin Interrupt Enable Register PienPIEN21 PIEN20PIPOL17 PIPOL16 PIPOL15 Video Port Pin Interrupt Polarity Register PipolPIPOL21 PIPOL20 PIPOL19 PIPOL13 PIPOL12VCTL3ACTLO PIPOL22VCTL3ACTHI PIPOL21Video Port Pin Interrupt Status Register Pistat VCTL2INT PISTAT22VCTL3INT PISTAT20Video Port Pin Interrupt Clear Register Piclr PICLR4PICLR21 PICLR22PICLR20 Vcxo Interpolated Control Port Overview Interface VIC Port Interface SignalsVIC Port Signal Direction Description Operational DetailsExample Values for Interpolation Rate VIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl VIC Control Register Vicctl Field DescriptionsGO bit can be written to at any time VIC Input Register Vicin Field Descriptions VIC Input Register VicinVicinbits VIC Clock Divider Register Vicdiv Field Descriptions VIC Clock Divider Register VicdivVicclkdiv Video Port Configuration Examples Example 1 Noncontinuous Frame Capture for 525/60 Format VCAIMGHSIZE2 * VCAIMGVSIZE2Frame VPVCASTOP1RMKVCAYSTOP1, VCAXSTOP1 VPVCASTRT1SSEENABLE, VCAXSTART1 Vpvcactlblkcapclear SPRU629 Vcayedmafrmcnt Edmaoptrmk Edmaoptprimedium Example 2 Noncontinuous Frame Display for 525/60 Format Vdhblnkstop Vdhblnkstart +Define vertical blanking bitVDVBITn reg values VDIMGHSIZE1 * VDIMGVSIZE1 Dmode VPVDFRMSZRMKVDFRMHEIGHT, Vdfrmwidth VPVDVBLKS2RMKVDVBLNKYSTART2, VDVBLNKXSTART2 VPVDVSYNE2RMKVDVSYNCYSTOP2, VDVSYNCXSTOP2 Vpvdstatfrmdclear Vdyedmafrmcnt Vdyedmaelecnt Example 2 Noncontinuous Frame Display for 525/60 Format EDMAOPT2DSYES Index Index-2 Index-3 Pin data set register Pdset Pin direction register Pdir Vcaevtct Vdhblnk Index-7 Vddefval Vddispevt Index-9 Ydsta Ydstb