Texas Instruments TMS320C64x DSP guide

4-44Video Display Port

SPRU629

Figure 4–37. Y/C Progressive Display Horizontal Timing Example

VCLKIN

			4								362						4										1280
															One Line																					Next Line
FPCOUNT	1280	1281	1282	1283	1284	1285	1286	1287	1349	1350	1429	1430	1644	1645	1646	1647	1648	1649	0	1	2	3	7	8	9	10	1270	1271	1272	1273	1276	1277	1278	1279	1280	1281	1282	1283
IPCOUNT	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	0	1	2	1262	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263	1263
VCTL1 (HBLNK)† §																						‡
VCTL1 (HSYNC)† §
VCLKOUT																											Display Image
																											Display Image
											Blanking																Active Video

VDOUT[9–0] §

DefY

FF.C

00.0

XY.0

80.0

FF.C

00.0

XY.0

DefY

Y1260

Y1261

Y1262

Y1263

DefY

FF.C

00.0

XY.0

VDOUT[19–0] §

DefCb

DefCr

FF.C

00.0

XY.0

10.0

FF.C

00.0

XY.0

DefCb

DefCr

DefCb

DefCr

DefCb

Cb0

Cr0

Cb1

Cr1

Cb2

Cr2

Cb630

Cr630

Cb631

Cr631

DefCb

DefCr

DefCb

DefCr

DefCb

DefCr

FF.C

00.0

XY.0

		EAV Blanking Data	SAV	EAV
FLCOUNT n –
	1		n	n + 1

FRMWIDTH = 1650		IMGHOFF1 = 8	HSYNCSTART = 1350
HBLNKSTART = 1280		IMGHSIZE1 = 1264	HSYNCSTOP = 1430
HBLNKSTOP = 1646		IMGHOFF2 = n/a
		IMGHSIZE2 = n/a

†Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00, HBLNK output when VCTL1S bit is set 01.

‡HBLNK operation when HBDLA bit in VDHBLNK is set to 1.

§ Diagram assumes a two VCLK pipeline delay between internal counters and output signals.

Display Timing Examples

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual 37. Y/C Progressive Display Horizontal Timing Example

Models: TMS320C64x DSP

SPRU629

Figure 4–37. Y/C Progressive Display Horizontal Timing Example

VCTL1 (HBLNK)† §

VCTL1 (HSYNC)† §

VCLKOUT

HSYNCSTOP = 1430

HBLNKSTOP = 1646

TMS320C64x DSP specifications