Video Port Control Registers

Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)

Bit

field

symval

Value

Description

3

SERRA

 

 

Channel A synchronization error interrupt detected bit.

 

 

 

 

BT.656 or Y/C capture mode – Synchronization parity error on

 

 

 

 

channel A. An SERRA typically requires resetting the channel

 

 

 

 

(RSTCH) or the port (VPRST).

 

 

 

 

Raw data mode or TSI capture mode – Not used.

 

 

NONE

0

No interrupt is detected.

 

 

CLEAR

1

Interrupt is detected. Bit is cleared.

 

 

 

 

 

2

CCMPA

 

 

Capture complete on channel A interrupt detected bit. (Data is not

 

 

 

 

in memory until the DMA transfer is complete.)

 

 

 

 

BT.656 or Y/C capture mode – CCMPA is set after capturing an

 

 

 

 

entire field or frame (when F1C, F2C, or FRMC in VCASTAT are

 

 

 

 

set) depending on the CON, FRAME, CF1, and CF2 control bits in

 

 

 

 

VCACTL.

 

 

 

 

Raw data mode – If RDFE bit is set, CCMPA is set when F1C,

 

 

 

 

F2C, or FRMC in VCASTAT is set (when the data counter = the

 

 

 

 

combined VCYSTOP/VCXSTOP value) depending on the CON,

 

 

 

 

FRAME, CF1, and CF2 control bits in VCACTL. If RDFE bit is not

 

 

 

 

set, CCMPA is set when FRMC in VCASTAT is set (when the data

 

 

 

 

counter = the combined VCYSTOP/VCXSTOP value).

 

 

 

 

TSI capture mode – CCMPA is set when FRMC in VCASTAT is set

 

 

 

 

(when the data counter = the combined VCYSTOP/VCXSTOP

 

 

 

 

value).

 

 

NONE

0

No interrupt is detected.

 

 

CLEAR

1

Interrupt is detected. Bit is cleared.

 

 

 

 

 

1

COVRA

 

 

Capture overrun on channel A interrupt detected bit. COVRA is set

 

 

 

 

when data in the FIFO was overwritten before being read out (by

 

 

 

 

the DMA).

 

 

NONE

0

No interrupt is detected.

 

 

CLEAR

1

Interrupt is detected. Bit is cleared.

 

 

 

 

 

0

Reserved

–

0

Reserved. The reserved bit location is always read as 0. A value

 

 

 

 

written to this field has no effect.

†For CSL implementation, use the notation VP_VPIS_field_symval

SPRU629

Video Port

2-29

Page 61 Page 63
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Image 62
Texas Instruments TMS320C64x DSP manual Serra, Vcactl
Page 61 Page 63

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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