Texas Instruments TMS320C64x DSP specification

Display Timing Examples

Figure 4–36. Raw Interlaced Display Vertical Timing Example

FLCOUNT		ILCOUNT
525		240
1		240
2		240
3		240
4		240
5	Field 1 Blanking	240
6	Field 1 Blanking	240

19		240
20		240
21	Field 1 Active	240
22	Field 1 Active	240
22		240
23		1
		2
	Field 1 Image
		239
262		240
263		240
264		240
265		240
266		240
267	Field 2 Blanking	240
268		240
269		240

282		240
283		240
284	Field 2 Active	240
285	Field 2 Active	240
285		240
286		1
		2
	Field 2 Image
524		239
525		240
1		240
		240

Active

Horizontal

Output

Default Value

FIFO Data

Default Value

FIFO Data

Default Value

IMGVOFF1 = 2	VBLNKXSTART1 = 720	VSYNCXSTART1 = 720	FLD1XSTART = 720
IMGVSIZE1 = 240	VBLNKYSTART1 = 1	VSYNCYSTART1 = 4	FLD1YSTART = 1
IMGVOFF2 = 3	VBLNKXSTOP1 = 720	VSYNCXSTOP1 = 720	FLD2XSTART = 360
IMGVSIZE2 = 240	VBLNKYSTOP1 = 21	VSYNCYSTOP1 = 7	FLD2YSTART = 263
FRMHEIGHT = 525	VBLNKXSTART2 = 360	VSYNCXSTART2 = 360
VBITSET1 = n/a	VBLNKYSTART2 = 263	VSYNCYSTART2 = 266	FBITSET = n/a
VBITCLR1 = n/a	VBLNKXSTOP2 = 360	VSYNCXSTOP2 = 360	FBITCLR = n/a
VBITSET2 = n/a	VBLNKYSTOP2 = 283	VSYNCYSTOP2 = 269
VBITCLR2 = n/a

†Assumes VCT2P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00, VBLNK output when VCTL2S bit is set 01.

4-42

Video Display Port

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual Raw Interlaced Display Vertical Timing Example

Models: TMS320C64x DSP

Figure 4–36. Raw Interlaced Display Vertical Timing Example

FLCOUNT

ILCOUNT

VBLNKYSTOP2 = 283

TMS320C64x DSP specifications