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Texas Instruments TMS320C64x DSP manual Display DMA Event Generation

Models: TMS320C64x DSP

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DMA Operation

Because the capture FIFOs may hold multiple thresholds worth of data, a problem arises at the boundaries between fields. Since Field 1 and Field 2 may have different threshold values, the amount of data in the FIFO required to generate the DMA event changes depending on the current capture field and the field of any outstanding DMA requests. Similarly, the threshold value loaded in the outgoing data counter needs to change depending on which field’s DMA event is being serviced (not which field is currently being captured). To prevent confusion at the field boundaries, the VCxEVTCT regis- ter is programmed to indicate the number of events to generate for each field. An event counter tracks how many events have been generated and indicates which threshold value to use in event generation and in the outgoing data counter. After the last Field 1 event has been generated, the DMA logic looks for FIFO > THRSHLD1 + THRSHLD2 to pregenerate the first Field 2 event. Once the last Field 1 event completes, the logic looks for FIFO > 2 ⋅ THRSHLD2 (assuming a Field 2 event is outstanding).

Some initial devices may require THRSHLD1 and THRSHLD2 to be set to the same value. Check the latest device errata, if you want to use different thresh- olds for the two fields.

2.3.2Display DMA Event Generation

Display DMA events are generated based on the amount of room available in the FIFO. The VDTHRLDn value indicates the level at which the FIFO has room to receive another DMA. If the FIFO has at least VDTHRLDn locations available, a DMA event is generated. Once a DMA event has been requested, another DMA event may not be generated until the servicing of the first DMA event has begun (as indicated by the first write to the FIFO by the DMA event service). If there is at least 2⋅ the threshold space still available in the FIFO after the first DMA service is begun (and the display event counter has not expired) then another DMA event may be generated. Thus, up to one DMA request may be outstanding.

An incoming data counter is loaded with the VDTHRLDn (or VDTHRLDn/2 for Cb and Cr FIFOs) value at the beginning of each DMA event service and counts down the incoming DMA doublewords When the counter reaches 0, the DMA event is complete. Figure 2–2 shows the display DMA event generation.

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Texas Instruments TMS320C64x DSP manual Display DMA Event Generation
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.