Video Output Filtering

4.4.2Chrominance Resampling Operation

Chrominance resampling computes chrominance values at sample points corresponding to output luminance samples based on the input interspersed chrominance samples. This filter performs the conversion between inter- spersed YCbCr 4:2:2 format and co-sited YCbCr 4:2:2 format. The vertical portion of the conversion from YCbCr 4:2:0 to interspersed YCbCr 4:2:2 must be performed in software.

The chrominance resampling filters calculate the implied value of Cb and Cr co-sited with luminance sample points based upon nearby interspersed Cb and Cr samples. The resulting values are clamped to between 01h and FEh before being output. Chrominance resampling is shown in Figure 4–19.

Figure 4–19. Chrominance Resampling

a b c d e

f

g h

i

j

k

l

YCbCr 4:2:2 interspersed source pixels

YCbCr 4:2:2 co–sited output results

–Luma (Y)

–Chroma (Cb/Cr)

sample

samples

Cb’f = (–3Cbab+ 33Cbcd + 101Cbef – 3Cbgh ) / 128 Cr’f = (–3Crab+ 33Crcd + 101Cref – 3Crgh ) / 128

4.4.3Scaling Operation

The 2⋅ -scaling mode is used to double the horizontal resolution of output luminance and chrominance data. This allows processed CIF resolution images to be output at full size. Vertical scaling must be performed in software. Scaling for co-sited source is shown in Figure 4–20 and scaling for interspersed source is shown in Figure 4–21.

For a co-sited source, the source luminance pixels are output unchanged for every even pixel (a, b, c, etc., in Figure 4–20). Odd luminance pixels (a’, b’, c’, etc.) are generated from neighboring source (even) pixels using a four tap fil- ter. The chrominance source pixels are output unchanged for every other even pixel (a, c, e, etc.). Other even output pixel (b, d, f, etc.) chrominance values are generated from neighboring source chrominance pixels using a four tap filter.

For an interspersed source, the luminance is output identically to the co-sited case. Chrominance output is generated using a four tap filter with one of two different coefficient sets depending on which source chrominance pixel the output pixel is closest.

Note that because input scaling is limited to 2x, full BT.656 width output is not achieved from CIF source images. The horizontal location of the reduced image can be adjusted using HOFFSET.

4-22

Video Display Port

SPRU629

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Texas Instruments TMS320C64x DSP manual Chrominance Resampling
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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