Capturing Data in TSI Capture Mode

6)Write to TSISTCMPL, TSISTCMPM, TSISTMSKL, and TSISTMSKM if needed to initiate an interrupt, based on STC absolute time.

7)Write to TSITICKS if an interrupt is desired every x cycles of STC.

8)Write to VPCTL to select TSI capture operation (TSI = 1).

9)Write to VPIE to enable overrun (COVRA) and capture complete (CCMPA) interrupts, if desired.

10)Write to VCACTL to set capture mode (CMODE = 010).

11)Set VCEN bit in VCACTL to enable capture.

12)Capture begins on the first VCLKINA rising edge when CAPENA and PACSTRT are valid. A DMA event is generated as triggered by VCATHRLD1. When the entire packet has been captured (DCOUNT = VCYSTOP and VCXSTOP combined value), the FRMC bit in VCASTAT is set causing the CCMPx bit in VPIS to be set. This gener- ates a DSP interrupt, if CCMPx is enabled in VPIE.

13)If continuous capture is enabled, the video port begins capturing again on the next VCLKINA rising edge when CAPENA and PACSTRT are valid. If noncontinuous capture is enabled, the next data packet is captured during which the DSP must clear the FRMC bit or further capture is disabled. If single frame capture is enabled, capture is disabled until the DSP clears the FRMC bit.

3.12.1 Handling FIFO Overrun Condition in TSI Capture Mode

In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVRx bit in VPIE enables overrun interrupt).

The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it should reconfigure DMA channel settings. The DMA channel must be reconfi- gured for capture of the next frame since the current frame transfer failed. Set- ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the channel. As long as the BLKCAP bit is set, the video capture channel ignores the incoming data but the internal data counter continues counting.

The BLKCAP bit should be cleared to 0 in order to continue capture. Clearing the BLKCAP bit takes effect on the next PACSTRT. (DMA events are still going to be blocked in the TSI packet in which the BLKCAP bit is cleared.)

3-48

Video Capture Port

SPRU629

Page 109 Page 111
Page 110
Image 110
Texas Instruments TMS320C64x DSP manual Handling Fifo Overrun Condition in TSI Capture Mode
Page 109 Page 111

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
Top Page Image Contents