Manuals / Texas Instruments / Computer Equipment / Network Card

Texas Instruments TMS320C64x DSP manual VSYNCYSTOP1, VSYNCXSTOP1

Models: TMS320C64x DSP

1 306

Download 306 pages 13.79 Kb

Page 225

Video Display Registers

4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)

The video display field 1 vertical synchronization end register (VDVSYNE1) controls the end of vertical synchronization in field 1. The VDVSYNE1 is shown in Figure 4–56 and described in Table 4–23.

Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.The VSYNC signal is deasserted whenever the frame line counter (FLCOUNT) is equal to VSYNCYSTOP1 and the frame pixel counter (FPCOUNT) is equal to VSYNCXSTOP1.

Figure 4–56. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)

31	28	27	16
	Reserved		VSYNCYSTOP1

	R-0		R/W-0
15	12	11	0

	Reserved		VSYNCXSTOP1

	R-0		R/W-0

Legend: R = Read only; R/W = Read/Write; -n= value after reset

Table 4–23. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Field Descriptions

Bit	field†	symval†	Value	Description
31–28	Reserved	–	0	Reserved. The reserved bit location is always read as
				0. A value written to this field has no effect.

27–16	VSYNCYSTOP1	OF(value)	0–FFFh	Specifies the line where VSYNC is deasserted for
				field 1.

15–12	Reserved	–	0	Reserved. The reserved bit location is always read as
				0. A value written to this field has no effect.

11–0	VSYNCXSTOP1	OF(value)	0–FFFh	Specifies the pixel where VSYNC is deasserted in
				field 1.

† For CSL implementation, use the notation VP_VDVSYNE1_field_symval

4-80

Video Display Port

SPRU629

Image 225

Texas Instruments TMS320C64x DSP manual VSYNCYSTOP1, VSYNCXSTOP1

Contents

Literature Number SPRU629 April Important Notice Read This First Trademarks Contents Video Capture Port Discusses operation of the video capture portVCASTOP1, VCBSTOP1 VCASTRT1, VCBSTRT1VCASTRT2, VCBSTRT2 VCASTOP2, VCBSTOP211.1 General Purpose I/O Operation VDVSYNE2Vcxo Interpolated Control Port Figures Xii Figures Xiii Video Port Tables Xvi Tables Xvii Topic OverviewVideo Port SPRU629 VCTL3 VCLK1 VCLK2 VCTL1 VCTL2Channel a Channel BDMA Interface Video Port FifoYsrca Cbsrca Crsrca Ysrcb Cbsrcb Crsrcb Video Capture Fifo ConfigurationsYsrca Ysrca Cbsrca Crsrca Y/C Video Capture Fifo ConfigurationYdsta Cbdst Crdst Video Display Fifo Configurations10-Bit Raw Video Display Fifo Configuration Ydstb YdstaVideo Port Registers 10. Y/C Video Display Fifo ConfigurationVideo Port Pin Mapping Video Capture Signal MappingUsage Raw Data Display Mode Video Display Signal MappingData Bus 10-Bit 16-Bit 20-Bit Mode Capture Mode BT.656 Raw DataVdin Bus Usage for Capture Modes Vdin Data Bus Usage for Capture ModesVdout Data Bus Usage for Display Modes Vdout Data Bus Usage for Display ModesVideo Port Reset Operation Power-On ResetPeripheral Bus Reset Capture Channel Reset Software Port ResetDisplay Channel Reset Interrupt Operation Capture DMA Event Generation DMA OperationFifo ≥ Capture DMA Event Generation Flow DiagramDisplay DMA Event Generation Display DMA Event Generation Flow Diagram DMA Size and Threshold Restrictions DMA Interface Operation Video Port Functionality Subsets ClocksVideo Port Functional Clocks Data Bus WidthVideo Port Throughput and Latency Fifo SizeVideo Capture Throughput Bit Bit Dense 10-Bit Y/C Video Capture Fifo CapacityVideo Display Throughput Raw Video Display Fifo CapacityBit Bit Dense 10/16-Bit 20-Bit Samples 5120 3840 2560 1280 Video Port Control Registers Video Port Control RegistersAcronym Register Name Section Video Port Control Register Vpctl Field Descriptions Video Port Control Register VpctlBit Value DescriptionVCLK2P None ClearNone Reverse None ActivelowVideo Port Operating Mode Selection Operating ModeVpctl Bit Video Port Status Register Vpstat Field Descriptions Video Port Status Register VpstatVideo Port Interrupt Enable Register Vpie Serrb CcmpbDcna Lfda Dcna Dcmp Video Port Interrupt Status Register VpisTick STC Lfda Sfda VINTA2 VINTA1 Serra Ccmpa CovraVcount = Ystop Vcbctl Out of the port. The DMA complete interrupt can be used to BT.656 or Y/C capture mode Lfda is set when long field Vcactl Video Capture Port Video Capture Mode Selection Video Capture Mode SelectionTSI Bit Cmode Bits Mode Description 1 BT.656 Capture Channels BT.656 Video Capture ModeBT.656 Video Timing Reference Codes 2 BT.656 Timing Reference CodesBT.656 Protection Bits Error Correction by Protection BitsLine Information Bits Protection Bits Received F, V, and H Bits3 BT.656 Image Window and Capture 010 011 100 101P 0 Bits Common Video Source Parameters Video Capture Parameters4 BT.656 Data Sampling Bit BT.656 Fifo Packing 5 BT.656 Fifo PackingVDIN9-0 / VDIN19-10 Cb Cr 0 Y Cb 1 Y Bit BT.656 Dense Fifo Packing Y/C Video Capture Mode 1 Y/C Capture Channels2 Y/C Timing Reference Codes 3 Y/C Image Window and Capture Bit Y/C Fifo Packing 4 Y/C Fifo PackingVDIN9-0 VDIN19-10 Little-Endian Packing Big-Endian Packing Bit Y/C Dense Fifo Packing Capture Determination and Notification BT.656 and Y/C Mode Field and Frame OperationBT.656 and Y/C Mode Capture Operation VC xCTL BitOperation VCxCTL Bit Vertical SynchronizationVertical Counter Reset Point Vertical Synchronization ProgrammingVC xCTL Bit VMode Vcount Operation Example EXC = Horizontal Synchronization Horizontal Counter Reset PointHorizontal Synchronization Programming VCxCTL Bit HModeHcount Operation Example EXC = Field Identification Programming Field IdentificationField Detect Method EAV codeShort and Long Field Detect 11.Field 1 Detection TimingVideo Input Filtering 10. Input Filter Mode SelectionInput Filter Modes Filter OperationScaling Operation Chrominance Resampling Operation13 /2 Scaled Co-Sited Filtering Edge Pixel Replication SAVEAV Xstart Xsize SAV 16. Capture Window Not Requiring Edge Pixel ReplicationAncillary Data Capture Horizontal Ancillary Hanc Data CaptureVertical Ancillary Vanc Data Capture Raw Data Capture Notification Raw Data Capture ModeRaw Data Fifo Packing 11. Raw Data Mode Capture Operation17 -Bit Raw Data Fifo Packing 19 -Bit Dense Raw Data Fifo Packing 21 -Bit Raw Data Fifo Packing TSI Capture Mode TSI Capture FeaturesTSI Data Capture TSI Capture Error Detection Synchronizing the System ClockVclkin Capen Pacstrt Ctmode PCR12. TSI Capture Mode Operation TSI Data Capture NotificationVcactl Bit Vclkin Writing to the FifoTSI TSI Fifo PerrReading from the Fifo Capture Line Boundary ConditionsFifo Ipcount = IMGHSIZE78 VclkoutCapturing Video in BT.656 or Y/C Mode Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Handling Fifo Overrun Condition in Raw Data Mode Capturing Data in TSI Capture ModeHandling Fifo Overrun Condition in TSI Capture Mode 13. Video Capture Control Registers Video Capture RegistersVideo Capture Channel x Status Register VCASTAT, Vcbstat Description Bit BT.656 or Y/C Mode Raw Data Mode TSI ModeValue BT.656 or Y/C Mode Raw Data Mode TSI Mode VcfldDetected Video Capture Channel a Control Register Vcactl Rdfe BlockFIELD1 FIELD2FDL EavfidV1EAV V0EAVCON ‡ HalfDescription Raw Data Mode TSI Mode Vcystart SSEVCXSTART/VCVBLNKP Vcvblnkp VcxstartVcxstop VcystopField† Symval† FFFh Last captured line Not used VINT2 VIF2 FSCL2VIF1 VINT1VIF2 SPRU629 VCTHRLD1 VCTHRLD2CAPEVTCT1 CAPEVTCT2Video Capture Channel B Control Register Vcbctl Vrst Hrst Vcen PK10B Lfde Sfde ResmplCON Frame CF2 CF1 F1C, F2C, and Frmc status bits, in VCBSTAT, are not EAV or Not used VCTL1 active edge Capture field Not used CON‡Enstc Tcken Sten Ctmode TSI Capture Control Register Tsictl24. TSI Capture Control Register Tsictl Field Descriptions Value BT.656, Y/C Mode TSI Mode Or Raw Data ModeTSI Clock Initialization LSB Register Tsiclkinitl BT.656, Y/C Mode TSI Mode Or Raw Data ModeInpcr Bit FieldTSI Clock Initialization MSB Register Tsiclkinitm InpcrmInpcre 42. TSI System Time Clock LSB Register Tsistclkl TSI System Time Clock LSB Register TsistclklTSI System Time Clock MSB Register Tsistclkm Pcre PcrmPcre ATC TSI System Time Clock Compare LSB Register Tsistcmpl45. TSI System Time Clock Compare MSB Register Tsistcmpm TSI System Time Clock Compare MSB Register TsistcmpmAtcm TSI System Time Clock Compare Mask LSB Register TsistmsklTSI System Time Clock Compare Mask MSB Register Tsistmskm Tickct TSI System Time Clock Ticks Interrupt Register TsiticksVideo Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw Data34. Video Capture Fifo Registers 35. Video Capture Fifo Registers FunctionVideo Display Port Video Display Mode Selection Video Display Mode SelectionDmode Bits Mode Description Image TimingNtsc Compatible Interlaced Display Interlaced Blanking Intervals and Video Areas Video Display Counters Progressive Blanking Intervals and Video AreaFpcount Horizontal Blanking and Horizontal Sync TimingFlcount Sync Signal GenerationVblnk VsyncPort Sync Operation External Sync OperationDisplay Timing Reference Codes BT.656 Video Display ModeLine Number BT.656 Frame Timing11.Digital Vertical F and V Transitions 3 BT.656 Image Display Blanking Codes12 -Bit BT.656 Fifo Unpacking 4 BT.656 Fifo Unpacking13 -Bit BT.656 Fifo Unpacking 14. BT.656 Dense Fifo Unpacking 1 Y/C Display Timing Reference Codes Y/C Video Display Mode2 Y/C Blanking Codes 3 Y/C Image Display4 Y/C Fifo Unpacking 16 -Bit Y/C Fifo Unpacking 17 -Bit Y/C Fifo Unpacking 18 -Bit Y/C Dense Fifo Unpacking Video Output Filtering Output Filter Mode SelectionOutput Filter Modes Vdctl Bit19. Chrominance Resampling 20 x Co-Sited Scaling 23. Luma Edge Replication Ancillary Data Display Raw Data Display ModeHorizontal Ancillary Hanc Data Display Vertical Ancillary Vanc Data DisplayRaw Data Fifo Unpacking Raw Mode RGB Output Support26 -Bit Raw Fifo Unpacking 28 -Bit Raw Fifo Unpacking 30 -Bit Raw 3/4 Fifo Unpacking Display Determination and Notification Video Display Field and Frame OperationCON Frame DF2 DF1 Display OperationVideo Display Event Generation Display Line Boundary Conditions 32. Display Line Boundary Example Interlaced BT.656 Timing Example Display Timing Examples33. BT.656 Interlaced Display Horizontal Timing Example SPRU629 34. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display Example 35. Raw Interlaced Display Horizontal Timing SPRU629 36. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example 37. Y/C Progressive Display Horizontal Timing Example SPRU629 38. Y/C Progressive Display Vertical Timing Example Displaying Video in BT.656 or Y/C Mode Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Displaying Video in Raw Data Mode Handling Underrun Condition of the Display Fifo Video Display Control Registers Video Display RegistersVideo Display Status Register Vdstat Video Display Status Register Vdstat Field Descriptions BT.656 and Y/C Mode Raw Data Mode Video Display Control Register VdctlVideo Display Control Register Vdctl Field Descriptions Blkdis Disable EnableFXS OutputValue BT.656 and Y/C Mode Raw Data Mode Blanking RgbxFlddis FrmdisVideo Display Frame Size Register Vdfrmsz FrmheightFrmwidth Hbdla Video Display Horizontal Blanking Register VdhblnkDelay HblnkstopHblnkstart VBLNKXSTART1 VBLNKYSTART1VBLNKXSTOP1 VBLNKYSTOP1Field† Symval† VBLNKXSTART2 VBLNKYSTART2VBLNKXSTOP2 VBLNKYSTOP2Video Display Field 1 Image Offset Register VDIMGOFF1 IMGVOFF1 IMGHOFF1Negoff Video Display Field 1 Image Size Register VDIMGSZ1 IMGVSIZE1IMGHSIZE1 Video Display Field 2 Image Offset Register VDIMGOFF2 IMGVOFF2IMGHOFF2 None Video Display Field 2 Image Size Register VDIMGSZ2 IMGVSIZE2IMGHSIZE2 Video Display Field 1 Timing Register VDFLDT1 FLD1YSTARTFLD1XSTART Video Display Field 2 Timing Register VDFLDT2 FLD2YSTARTFLD2XSTART Incpix Video Display Threshold Register VdthrldVDTHRLD1 VDTHRLD2Video Display Horizontal Synchronization Register Vdhsync HsyncstopHsyncstart VSYNCXSTART1 VSYNCYSTART1VSYNCXSTOP1 VSYNCYSTOP1VSYNCXSTART2 VSYNCYSTART2VSYNCXSTOP2 VSYNCYSTOP2Vrld Video Display Counter Reload Register VdreloadHrld CrldVideo Display Display Event Register Vddispevt DISPEVT2DISPEVT1 Clipchigh Video Display Clipping Register VdclipClipyhigh Clipylow ClipclowVideo Display Default Display Value Register Vddefval Crdefval CbdefvalYdefval Crdefval Defval64. Video Display Vertical Interrupt Register Vdvint Video Display Vertical Interrupt Register VdvintVideo Display Field Bit Register Vdfbit FbitsetFbitclr VBITSET1 VBITCLR1Field† Symval† VBITSET2 VBITCLR2Field† Symval† Video Display Registers Recommended Values 34. Video Display Register Recommended ValuesRegister Field 525/60 Value 625/50 Value VDVSYNE2 VSYNCXSTOP2 VDVSYNS2 VSYNCXSTART2Vdfbit Fbitclr Fbitset VDVBIT1 VBITSET135. Video Display Fifo Registers Video Display Fifo Registers36. Video Display Fifo Registers Function Register BT.656 or Y/C Raw DataGpio Registers General Purpose I/O OperationVideo Port Registers Gpio RegistersType Video Port Peripheral Identification Register VppidClass Revision ClassSoft Free Video Port Peripheral Control Register PCRSoft PerenStop CompVideo Port Pin Function Register Pfunc Field Descriptions Video Port Pin Function Register PfuncPFUNC22 NormalPFUNC10 PFUNC20VDATA10TO19 PFUNC0Video Port Pin Direction Register Pdir Field Descriptions Video Port Pin Direction Register PdirPDIR22 VCTL3INVCTL2IN PDIR21VCTL2OUT PDIR20VDATA8TO9IN PDIR8VDATA8TO9OUT PDIR4PDIN20 Video Port Pin Data Input Register PdinPDIN12 PDIN7 PDIN6Video Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Output Register Pdout Video Port Pin Data Out Register Pdout Field Descriptions PDOUT21PDOUT20 Video Port Pin Data Set Register Pdset Video Port Pin Data Set Register Pdset Field Descriptions PDSET21PDSET20 Video Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register PdclrVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Interrupt Enable Register Pien Video Port Pin Interrupt Enable Register PienPIEN20 PIEN21PIPOL21 PIPOL20 PIPOL19 Video Port Pin Interrupt Polarity Register PipolPIPOL17 PIPOL16 PIPOL15 PIPOL13 PIPOL12VCTL3ACTHI PIPOL22VCTL3ACTLO PIPOL21Video Port Pin Interrupt Status Register Pistat VCTL3INT PISTAT22VCTL2INT PISTAT20PICLR4 Video Port Pin Interrupt Clear Register PiclrPICLR22 PICLR21PICLR20 Vcxo Interpolated Control Port Overview VIC Port Signal Direction Description VIC Port Interface SignalsInterface Operational DetailsExample Values for Interpolation Rate Enabling VIC Port VIC Port RegistersVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register VicctlGO bit can be written to at any time VIC Input Register Vicin VIC Input Register Vicin Field DescriptionsVicinbits VIC Clock Divider Register Vicdiv VIC Clock Divider Register Vicdiv Field DescriptionsVicclkdiv Video Port Configuration Examples VCAIMGHSIZE2 * VCAIMGVSIZE2 Example 1 Noncontinuous Frame Capture for 525/60 FormatFrame VPVCASTOP1RMKVCAYSTOP1, VCAXSTOP1 VPVCASTRT1SSEENABLE, VCAXSTART1 Vpvcactlblkcapclear SPRU629 Vcayedmafrmcnt Edmaoptrmk Edmaoptprimedium Vdhblnkstop Vdhblnkstart + Example 2 Noncontinuous Frame Display for 525/60 FormatDefine vertical blanking bitVDVBITn reg values VDIMGHSIZE1 * VDIMGVSIZE1 Dmode VPVDFRMSZRMKVDFRMHEIGHT, Vdfrmwidth VPVDVBLKS2RMKVDVBLNKYSTART2, VDVBLNKXSTART2 VPVDVSYNE2RMKVDVSYNCYSTOP2, VDVSYNCXSTOP2 Vpvdstatfrmdclear Vdyedmafrmcnt Vdyedmaelecnt Example 2 Noncontinuous Frame Display for 525/60 Format EDMAOPT2DSYES Index Index-2 Index-3 Pin data set register Pdset Pin direction register Pdir Vcaevtct Vdhblnk Index-7 Vddefval Vddispevt Index-9 Ydsta Ydstb