Texas Instruments TMS320C64x DSP manual Video Port Status Register Vpstat

Video Port Control Registers

2.7.2Video Port Status Register (VPSTAT)

The video port status register (VPSTAT) indicates the current condition of the video port. The VPSTAT is shown in Figure 2–4 and described in Table 2–7.

Figure 2–4. Video Port Status Register (VPSTAT)

31					16
	Reserved
	R-0
15	4	3	2	1	0
Reserved		DCDIS	HIDATA	Reserved
R-0		R-x	R-x		R-0

Legend: R = Read only; -n= value after reset; -x = value is determined by chip-level configuration

Table 2–7. Video Port Status Register (VPSTAT) Field Descriptions

Bit	field†	symval†	Value	Description
31–4	Reserved	–	0	Reserved. The reserved bit location is always read as 0. A value
				written to this field has no effect.
3	DCDIS			Dual-channel disable bit. The default value is determined by the
				chip-level configuration.
		ENABLE	0	Dual-channel operation is enabled.
		DISABLE	1	Port muxing selections prevent dual-channel operation.
2	HIDATA			High data bus half. HIDATA does not affect video port operation
				but is provided to inform you which VDATA pins may be controlled
				by the video port GPIO registers. HIDATA is never set unless
				DCDIS is also set. The default value is determined by the
				chip-level configuration.
		NONE	0
		USE	1	Indicates that another peripheral is using VDATA[9–0] and the
				video port channel A (VDIN[9–0] or VDOUT[9–0]) is muxed onto
				VDATA[19–10].
1–0	Reserved	–	0	Reserved. The reserved bit location is always read as 0. A value
				written to this field has no effect.

† For CSL implementation, use the notation VP_VPSTAT_field_symval

2-20 Video Port SPRU629