Video Display Field and Frame Operation

 

Table 4–4. Display Operation

 

 

 

 

 

 

 

 

VDCTL Bit

 

 

 

 

 

 

 

 

 

CON

FRAME

DF2

DF1

Operation

 

 

 

 

 

 

 

0

0

0

0

Reserved

 

0

0

0

1

Noncontinuous field 1 display. Display only field 1. F1D is set after

 

 

 

 

 

field 1 display and causes DCMPx to be set. The F1D bit must be

 

 

 

 

 

cleared by the DSP or a DCNA interrupt occurs. (The DSP has the en-

 

 

 

 

 

tire field 2 time to clear F1D before next field 1 begins.) Can also be

 

 

 

 

 

used for single progressive frame display (internal timing codes only).

 

 

 

 

 

(The DSP has vertical blanking time to clear F1D before next frame

 

 

 

 

 

begins.)

 

0

0

1

0

Noncontinuous field 2 display. Display only field 2. F2D is set after

 

 

 

 

 

field 2 display and causes DCMPx to be set. The F2D bit must be

 

 

 

 

 

cleared by the DSP or a DCNA interrupt occurs. (The DSP has the en-

 

 

 

 

 

tire field 1 time to clear F2D before next field 2 begins.)

 

0

0

1

1

Noncontinuous field 1 and field 2 display. Display both fields. F1D is set

 

 

 

 

 

after field 1 display and causes DCMPx to be set. The F1D bit must be

 

 

 

 

 

cleared by the DSP before the next field 1 display or a DCNA interrupt

 

 

 

 

 

occurs. (The DSP has the entire field 2 time to clear F1D before next

 

 

 

 

 

field 1 begins.) F2D is set after field 2 display and also causes DCMPx

 

 

 

 

 

to be set. The F2D bit must be cleared by the DSP before the next

 

 

 

 

 

field 2 display or a DCNA interrupt occurs. (The DSP has the entire

 

 

 

 

 

field 1 time to clear F2D before next field 2 begins.)

 

0

1

0

0

Noncontinuous frame display. Display both fields. FRMD is set after

 

 

 

 

 

field 2 display and causes DCMPx to be set. A DCNA interrupt occurs

 

 

 

 

 

upon completion of the next frame unless the FRMD bit is cleared. (The

 

 

 

 

 

DSP has the entire next frame time to clear FRMD.)

 

0

1

0

1

Noncontinuous progressive frame display. Display field 1. FRMD is set

 

 

 

 

 

after field 1 display and causes DCMPx to be set. A DCNA interrupt

 

 

 

 

 

occurs upon completion of the next frame unless the FRMD bit is

 

 

 

 

 

cleared. (The DSP has the entire next frame time to clear FRMD.) If

 

 

 

 

 

external control signals are used, they must follow progressive format.

 

0

1

1

0

Reserved

 

0

1

1

1

Single frame display. Display both fields. FRMD is set after field 2 dis-

 

 

 

 

 

play and causes DCMPx to be set. A DCNA interrupt occurs unless the

 

 

 

 

 

FRMD bit is cleared. (The DSP has the field 2 to field 1 vertical blank-

 

 

 

 

 

ing time to clear FRMD.)

 

1

0

0

0

Reserved

 

1

0

0

1

Continuous field 1 display. Display only field 1. F1D is set after field 1

 

 

 

 

 

display and causes DCMPx to be set (DCMPx interrupt can be dis-

 

 

 

 

 

abled). No DCNA interrupt occurs, regardless of the state of F1D.

 

 

 

 

 

 

 

SPRU629

Video Display Port

4-31

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Texas Instruments TMS320C64x DSP manual Display Operation, CON Frame DF2 DF1
Page 175 Page 177

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

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In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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