Texas Instruments TMS320C64x DSP manual CAPEVTCT2, CAPEVTCT1

Video Capture Registers

3.13.9 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT)

The video capture channel x event count register (VCAEVTCT, VCBEVTCT) is programmed with the number of DMA events to be generated for each capture field. VCxEVTCT is shown in Figure 3–37 and described in Table 3–22.

An event counter tracks how many events have been generated and indicates which threshold value (VCTHRLD1 or VCTHRLD2 in VCxTHRLD) to use in event generation and in the outgoing data counter. Once the CAPEVTCTn number of events have been generated, the DMA logic switches to the other threshold value. See section 2.3.1.

Figure 3–37. Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT)

31	28	27	16
	Reserved		CAPEVTCT2
	R-0		R/W-0
15	12	11	0
	Reserved		CAPEVTCT1
	R-0		R/W-0

Legend: R = Read only; R/W = Read/Write; -n= value after reset

Table 3–22. Video Capture Channel x Event Count Register (VCxEVTCT) Field Descriptions

				Description
Bit	field†	symval†	Value	BT.656 or Y/C Mode	Raw Data Mode	TSI Mode
31–28	Reserved	–	0	Reserved. The reserved bit location is always read as 0. A
				value written to this field has no effect.
27–16	CAPEVTCT2	OF(value)	0–FFFh	Number of DMA event	Not used.	Not used.
				sets (YEVT, CbEVT,
				CrEVT) to be generated
				for field 2 capture.
15–12	Reserved	–	0	Reserved. The reserved bit location is always read as 0. A
				value written to this field has no effect.
11–0	CAPEVTCT1	OF(value)	0–FFFh	Number of DMA event	Not used.	Not used.
				sets (YEVT, CbEVT,
				CrEVT) to be generated
				for field 1 capture.

† For CSL implementation, use the notation VP_VCxEVTCT_CAPEVTCTn_symval

SPRU629 Video Capture Port 3-67