Ancillary Data Display / Raw Data Display Mode

4.5 Ancillary Data Display

The following sections discuss ancillary data display. No special previsions are made for the display of horizontal ancillary (HANC) or vertical ancillary (VANC), also called vertical blanking interval (VBI), data.

4.5.1Horizontal Ancillary (HANC) Data Display

HANC data can be displayed using the normal video display mechanism by programming IMGHSIZEn to occur prior to the SAV code. The HANC data including the ancillary data header must be part of the YCbCr separated data in the FIFOs. The VCTHRLD value and DMA size must be programmed to comprehend the additional samples. You must disable scaling and chroma re- sampling when including the display of HANC data to prevent data corruption.

4.5.2Vertical Ancillary (VANC) Data Display

VANC (or VBI) data is commonly used for such features as teletext and closed- captioning. No special provisions are made for the display of VBI data. VBI data may be displayed using the normal display mechanism by programming IMGVOFF to occur before the first line of active video on the first line of desired VBI data. Note that the VBI data must be YCbCr separated. You must disable scaling and chroma resampling when the display of VBI data is desired or the data will be corrupted by the filters.

4.6 Raw Data Display Mode

The raw data display modes are intended to output data to a RAMDAC or other D/A-type device. This is typically RGB formatted data. No timing information is inserted into the output data stream; instead, selectable control signals are output to indicate timing. Raw data display includes a synchronized dual channel option. This allows channel B to output a separate data stream using the same clock and control as channel A. This mode is useful when used with a second video port in systems that require 24-bit to 30-bit RGB output.

The raw data mode uses a single FIFO of 5120 bytes for storage of output data. The FIFO is filled by DMAs writing to the Y FIFO destination register A (YDSTA). DMAs are requested using the YEVTA event. In raw sync mode (RSYNC bit is set), the FIFO is split into 2560-byte channel A and B buffers. The channel B FIFO is filled by DMAs using the Y FIFO destination register B (YDSTB) as a destination. Both YEVTA and YEVTB events are generated using the channel A timing control.

SPRU629

Video Display Port

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Texas Instruments TMS320C64x DSP Ancillary Data Display, Raw Data Display Mode, Horizontal Ancillary Hanc Data Display
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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