DMA Operation

A DMA event counter is used to track the number of DMA events generated in each field as programmed in the VDDISPEVT register. The DISPEVT1 or DISPEVT2 value (depending on the current display field) is loaded at the start of each field. The event counter then decrements with each DMA event gener- ation until it reaches 0, at which point no more DMA events are generated until the next field begins. Once the last line of data for a field has been requested, the DMA logic stops generating events until the field is complete in case the CPU needs to modify the DMA address pointers.

For BT.656 and Y/C modes, there are three FIFOs, one for each of the Y, Cb, and Cr color components. Each FIFO generates its own DMA event; therefore, the DMA event state and FIFO thresholds for each FIFO are tracked indepen- dently. (The Cb and Cr FIFOs use a threshold value of ½ VDTHRLD).

2.3.3DMA Size and Threshold Restrictions

The video port FIFOs are 64-bits wide and always read or write 64 bits at a time. For this reason, DMA accesses must always be an even number of words in length. It is expected that in most cases the threshold size is set to the line length (rounded up to the next doubleword). This always works because differ- ent lines are not packed together within a doubleword and the Cb and Cr thresholds (½ VCTHRLDx/VDTHRLD) are always rounded up to the double- word.

For example, in 8-bit BT.656 capture mode with a line length of 712 (Y), setting the threshold to the line length results in a VCTHRLD of 712 pixels ⋅ 1 bytes/ pixel ⋅ doubleword/8 bytes = 89 doublewords. The Cb and Cr FIFOs contain half the data (44.5 doublewords) so their thresholds are set to 45 double- words. Therefore, the Cb and Cr DMAs each transmit an extra 4 bytes at the end of each line.

If a multihorizontal line length threshold is desired (2 lines, for example) then the chosen line length must round up to an even number of doublewords so that it is evenly divisible by 2. If this is not the case, then the Cb and Cr FIFO transfers are corrupted. For the multiline case, consider the same 8-bit BT.656 capture mode with a line length of 712 (Y). If the threshold is set for 2 lines, this results in a VCTHRLD value of 2 ⋅ 89 = 178 doublewords. The actual Cb/Cr line length is 44.5 doublewords that requires a length of 45. To transfer 2 lines requires 2 ⋅ 45 = 90 doublewords. However, for this VCTHRLD, the DMA logic would calculate the Cb/Cr threshold size as 178/2 = 89 doublewords, which is 1 doubleword off. This can be corrected by increasing the line length to 720 pixels (and ignoring the extra captured pixels) or decreasing it to 704 pixels.

2-10

Video Port

SPRU629

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Texas Instruments TMS320C64x DSP manual DMA Size and Threshold Restrictions
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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