FLD2YSTART, FLD2XSTART | Texas Instruments TMS320C64x DSP manual

Video Display Registers

4.12.14 Video Display Field 2 Timing Register (VDFLDT2)

The video display field 2 timing register (VDFLDT2) sets the timing of the field identification signal. The VDFLDT2 is shown in Figure 4–52 and described in Table 4–19.

In raw data mode, the FLD signal is asserted whenever the frame line counter (FLCOUNT) is equal to FLD2YSTART and the frame pixel counter (FPCOUNT) is equal to FLD2XSTART (this is shown in Figure 4–6, page 4-7).

In BT.656 and Y/C mode, the FLD signal is asserted to indicate field 2 display whenever FLCOUNT = FLD2YSTART and FPCOUNT = FLD2XSTART. The FLD output is completely independent of the timing control codes. The F bit in the EAV/SAV codes is controlled by the VDFBIT register.

Figure 4–52. Video Display Field 2 Timing Register (VDFLDT2)

31	28	27	16
	Reserved		FLD2YSTART

	R-0		R/W-0
15	12	11	0

	Reserved		FLD2XSTART

	R-0		R/W-0

Legend: R = Read only; R/W = Read/Write; -n= value after reset

Table 4–19. Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions

Bit	field†	symval†	Value	Description
31–28	Reserved	–	0	Reserved. The reserved bit location is always read as 0.
				A value written to this field has no effect.

27–16	FLD2YSTART	OF(value)	0–FFFh	Specifies the first line of field 2. (The line where FLD is
				asserted.)

15–12	Reserved	–	0	Reserved. The reserved bit location is always read as 0.
				A value written to this field has no effect.

11–0	FLD2XSTART	OF(value)	0–FFFh	Specifies the pixel on the first line of field 2 where the FLD
				output is asserted.

† For CSL implementation, use the notation VP_VDFLDT2_field_symval

SPRU629

Video Display Port

4-75

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

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Texas Instruments TMS320C64x DSP manual Video Display Field 2 Timing Register VDFLDT2, FLD2YSTART

Models: TMS320C64x DSP

4.12.14 Video Display Field 2 Timing Register (VDFLDT2)

Figure 4–52. Video Display Field 2 Timing Register (VDFLDT2)

FLD2YSTART

FLD2XSTART

Bit

field†

Value

OF(value)

OF(value)

SPRU629

TMS320C64x DSP specifications