Hblnkstop, Delay, Hblnkstart | Texas Instruments TMS320C64x DSP

Video Display Registers

Table 4–9. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions

				Description
Bit	field†	symval†	Value	BT.656 and Y/C Mode	Raw Data Mode
31–28	Reserved	–	0	Reserved. The reserved bit location is always read as 0.
				A value written to this field has no effect.

27–16	HBLNKSTOP	OF(value)	0–FFFh	Location of SAV code and	Ending pixel (FPCOUNT)
				HBLNK inactive edge	of blanking video area
				within the line. HBLNK	(HBLNK inactive) within
				inactive edge may be	the line.
				optionally delayed by
				4 VCLKs.

15	HBDLA			Horizontal blanking delay enable bit.
		NONE	0	Horizontal blanking delay	Not used.
		NONE	0	Horizontal blanking delay	Not used.
				is disabled.
		DELAY	1	HBLNK inactive edge is	Not used.
				delayed by 4 VCLKs.

14–12	Reserved	–	0	Reserved. The reserved bit location is always read as 0.
				A value written to this field has no effect.

11–0	HBLNKSTART	OF(value)	0–FFFh	Location of EAV code and	Starting pixel (FPCOUNT)
				HBLNK active edge within	of blanking video area
				the line.	(HBLNK active) within the
					line.

†For CSL implementation, use the notation VP_VDHBLNK_field_symval

4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)

The video display field 1 vertical blanking start register (VDVBLKS1) controls the start of vertical blanking in field 1. The VDVBLKS1 is shown in Figure 4–43 and described in Table 4–10.

In raw data mode, VBLNK is asserted whenever the frame line counter (FLCOUNT) is equal to VBLNKYSTART1 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTART1 (this is shown in Figure 4–6, page 4-7).

In BT.656 and Y/C mode, VBLNK is asserted whenever FLCOUNT = VBLNKYSTART1 and FPCOUNT = VBLNKXSTART1. This VBLNK output control is completely independent of the timing control codes. The V bit in the EAV/SAV codes for field 1 is controlled by the VDVBIT1 register.

4-62

Video Display Port

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual Hblnkstop, Delay, Hblnkstart

Models: TMS320C64x DSP

Bit

field†

Value

HBLNKSTOP

OF(value)

HBDLA

DELAY

HBLNKSTART

OF(value)

TMS320C64x DSP specifications