Texas Instruments TMS320C64x DSP manual Capture Line Boundary Conditions, Reading from the Fifo

TSI Capture Mode / Capture Line Boundary Conditions

Figure 3–27. TSI Timestamp Format (Big Endian)

63	56	55		48	47			40	39			32
	PCR(7–0)		PCR(15–8)			PCR(23–16)				PCR(31–24)
31			25	24	23					18	17	16
	PCR extension (6–0)			PCR32			Reserved				PCR ext (8–7)
15				8	7	6		5				0
	Reserved				PERR		PSTERR			Reserved

3.8.7Reading from the FIFO

The YSRCA location is associated with the TSI capture buffer. The YSRCA location is a read-only pseudo-register and is used to access the TSI data samples stored in the buffer.

The captured data packet size is set by VCASTOP. The VCXSTOP and VCYSTOP bits set the 24-bits of TSI packet size (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits). Capture is complete and the FRMC bit is set when the data counter equals the combined VCYSTOP and VCXSTOP value.

The video port generates a YEVT after the specified number of new samples has been captured in the buffer. The number of samples required to generate YEVT is programmable and is set in the VCTHRLD1 bits of VCATHRLD. VCTHRLD1 should be set to the packet size plus 8 bytes of timestamp. On every YEVT, the DMA should move data from the buffer to the DSP memory. When moving data from the buffer to the DSP memory, the DMA should use the memory address of the YSRCA location as a source address.

3.9 Capture Line Boundary Conditions

In order to simplify DMA transfers, FIFO doublewords must not contain data from more than one capture line. This means that a FIFO write must be performed whenever 8 bytes have been received or when the line complete condition (HCOUNT = VCXSTOP) occurs. Thus, every captured line begins on a doubleword boundary and non-doubleword length lines are padded at the end. An example is shown in Figure 3–28.

3-42 Video Capture Port SPRU629