Texas Instruments TMS320C64x DSP manual Video Capture Channel B Control Register Vcbctl

Video Capture Registers

3.13.10 Video Capture Channel B Control Register (VCBCTL)

Video capture is controlled by the video capture channel B control register (VCBCTL) shown in Figure 3–38 and described in Table 3–23.

Figure 3–38. Video Capture Channel B Control Register (VCBCTL)

31	30	29								24
RSTCH	BLKCAP					Reserved
R/WS-0	R/W-1						R-0
23			21	20	19		18		17	16
	Reserved			FINV		Reserved			VRST	HRST
	R-0			R/W-0			R-0		R/W-1	R/W-0
15	14		13	12		11	10		9	8
VCEN	PK10B			LFDE		SFDE		RESMPL	Reserved	SCALE
R/W-0	R/W-0			R/W-0		R/W-0		R/W-0	R-0	R/W-0
7	6	5		4	3		2		1	0
CON	FRAME	CF2		CF1		Reserved			CMODE
R/W-0	R/W-0	R/W-1		R/W-1			R-0		R/W-0

Legend: R = Read only; R/W = Read/Write; WS = Write 1 to reset, write of 0 has no effect; -n= value after reset

Table 3–23. Video Capture Channel B Control Register (VCBCTL)

Field Descriptions

					Description
Bit	field†	symval†	Value	BT.656 or Y/C Mode	Raw Data Mode	TSI Mode
31	RSTCH			Reset channel bit. Write 1 to reset the bit, a write of 0 has no
				effect.
		NONE	0	No effect.
		RESET	1	Resets the channel by blocking further DMA event generation
				and flushing the FIFO upon completion of any pending DMAs.
				Also clears the VCEN bit. All channel registers are set to their
				initial values. RSTCH is autocleared after channel reset is complete.

† For CSL implementation, use the notation VP_VCBCTL_field_symval

‡For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.

3-68 Video Capture Port SPRU629