4 BT.656 Fifo Unpacking | Texas Instruments TMS320C64x DSP specs

BT.656 Video Display Mode

4.2.4BT.656 FIFO Unpacking

Display data is always packed into the FIFOs in 64-bit words and must be unpacked before being sent to the video display data pipeline. The unpacking and byte ordering is dependant upon the display data size and the device endian mode. For little-endian operation (default), data is unpacked from right to left; for big-endian operation, data is unpacked from left to right.

The 8-bit BT.656 mode uses three FIFOs for color separation. Four samples are unpacked from each word as shown in Figure 4–12.

Figure 4–12. 8-Bit BT.656 FIFO Unpacking

Y FIFO

VCLKOUT

VDOUT[9–2]

Cb 0 Y 0

Cr 0

Y 1 Cb 1

Y 2 Cr 1

Y 3 Cb 2

Y 4 Cr 2

Y 5

5655

4847

4039

3231

2423

1615

Y 31

Y 30

Y 29

Y 28

Y 27

Y 26

Y 25

Y 24

Y 23

Y 22

Y 21

Y 20

Y 19

Y 18

Y 17

Y 16

Y 15

Y 14

Y 13

Y 12

Y 11

Y 10

Y 9

Y 8

Y 7

Y 6

Y 5

Y 4

Y 3

Y 2

Y 1

Y 0

Cb FIFO

5655

4847

4039

3231

2423

1615

Cb 15

Cb 14

Cb 13

Cb 12

Cb 11

Cb 10

Cb 9

Cb 8

Cb 7

Cb 6

Cb 5

Cb 4

Cb 3

Cb 2

Cb 1

Cb 0

Cr FIFO

5655

4847

4039

3231

2423

1615

Cr 15

Cr 14

Cr 13

Cr 12

Cr 11

Cr 10

Cr 9

Cr 8

Cr 7

Cr 6

Cr 5

Cr 4

Cr 3

Cr 2

Cr 1

Cr 0

Little-Endian Unpacking

Y FIFO

5655

4847

4039

3231

2423

1615

Y 24

Y 25

Y 26

Y 27

Y 28

Y 29

Y 30

Y 31

Y 16

Y 17

Y 18

Y 19

Y 20

Y 21

Y 22

Y 23

Y 8

Y 9

Y 10

Y 11

Y 12

Y 13

Y 14

Y 15

Y 0

Y 1

Y 2

Y 3

Y 4

Y 5

Y 6

Y 7

	63	5655		4847	4039	3231	2423	1615	8	7	0
	Cb 8		Cb 9		Cb 10	Cb 11	Cb 12	Cb 13	Cb 14		Cb 15
Cb FIFO	Cb 0		Cb 1		Cb 2	Cb 3	Cb 4	Cb 5	Cb 6		Cb 7
Cb FIFO	63	5655		4847	4039	3231	2423	1615	8	7	0
	63	5655		4847	4039	3231	2423	1615	8	7	0
	Cr 8		Cr 9		Cr 10	Cr 11	Cr 12	Cr 13	Cr 14		Cr 15
Cr FIFO	Cr 0		Cr 1		Cr 2	Cr 3	Cr 4	Cr 5	Cr 6		Cr 7
Cr FIFO

Big-Endian Unpacking

SPRU629

Video Display Port

4-13

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual 4 BT.656 Fifo Unpacking, Bit BT.656 Fifo Unpacking

Models: TMS320C64x DSP

4.2.4BT.656 FIFO Unpacking

Figure 4–12. 8-Bit BT.656 FIFO Unpacking

Y FIFO

VCLKOUT

SPRU629

TMS320C64x DSP specifications