BT.656 Video Display Mode

4.2.2Blanking Codes

The time between the EAV and SAV code on each line represents the horizontal blanking interval. During this time, the video port outputs digital video blanking values. These values are 10.0h for luma (Y) samples and 80.0h for chroma (Cb/Cr) samples. These values are also output during the active line period of vertical blanking (between SAV and EAV when V = 1). In addition, if the DVEN bit in VDCTL is cleared to 0, the blanking values are output during the portion of active video lines that are not a part of the displayed image.

4.2.3BT.656 Image Display

For BT.656 display mode, the FIFO buffer is divided into three sections. One FIFO is 2560-bytes deep and is used for the storage of Y output samples; the other two FIFOs are each 1280-bytes deep and are dedicated for storage of Cb and Cr samples. Each FIFO has a memory-mapped location associated with it; YDST, CBDST, and CRDST. The pseudo-registers are write-only and are used by DMAs to fill the FIFOs with output data. The video display module multiplexes the data from the three FIFOs to generate the output CbYCrY data stream.

If video display is enabled, the video display module uses the YEVT, CbEVT, and CrEVT events to notify the DMA controller that data needs to be placed into the display FIFOs. The number of pixels required to generate the events is set by the VDTHRLD bits in VDTHRLD (VTHRLD must be an even number). The video display module generates the event signals when the display buffer holds less than the VDTHRLD number of pixels and the DEVTCT counter has not expired. On every YEVT, the DMA should move data from DSP memory to the Y buffer, using the Y FIFO destination register (YDST) content as the destination address. On every CbEVT, the DMA should move data from DSP memory to the Cb buffer, using the Cb FIFO destination register (CBDST) content as the destination address. On every CrEVT, the DMA should move data from DSP memory to the Cr buffer, using the Cr FIFO destination register (CRDST) content as the destination address. The DMA transfer size for the Y buffer is twice the size of the DMA for the Cb or Cr buffers.

4-12

Video Display Port

SPRU629

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Texas Instruments TMS320C64x DSP manual Blanking Codes, 3 BT.656 Image Display
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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