Manuals / Texas Instruments / Computer Equipment / Network Card

Texas Instruments TMS320C64x DSP manual Capturing Video in BT.656 or Y/C Mode

Models: TMS320C64x DSP

1 306
Download 306 pages 13.79 Kb
Page 106
Image 106

Capturing Video in BT.656 or Y/C Mode

3.10 Capturing Video in BT.656 or Y/C Mode

In order to capture video in the BT.656 or Y/C format, the following steps are needed:

1)Set the last pixel to be captured in VCxSTOP1 and VCxSTOP2 (set the VCXSTOP and VCYSTOP bits).

2)Set the first pixel to be captured in VCxSTRT1 and VCxSTRT2 (set the VCXSTART and VCYSTART bits).

3)Write to VCxTHRLD to set the capture threshold. Every time the number of received pixels reaches the number specified by the VCTHRLD1 bits, a YEVTx, CbEVTx, and CrEVTx are generated by the video capture module. The VCTHRLD1 bits value must be an even number.

4)Configure a DMA channel to move data from YSRCx to a destination in the DSP memory. The channel transfers should be triggered by the YEVTx. The size of the transfers should be set to VCTHRLD1/4 for 8-bit mode, VCTHRLD1/2 for 10-bit mode, or VCTHRLD1/3 for dense 10-bit mode. (This is because 4, 2, or 3 pixels are packed per FIFO word and the DMA is moving 32-bit words from YSRCx to the memory). The DMA must start on a doubleword boundary and move an even number of words.

5)Configure a DMA channel to move data from CBSRCx to a destination in the DSP memory. The channel transfers should be triggered by the CbEVTx. The size of the transfers should be set to VCTHRLD1/8 for 8-bit mode, VCTHRLD1/4 for 10-bit mode, or VCTHRLD1/6 for dense 10-bit mode. (This is because 4, 2, or 3 pixels are packed per FIFO word, the DMA is moving 32-bit words from CBSRCx to the memory, and there are half the number of pixels in the Cb FIFO as in the Y FIFO.) The DMA must start on a doubleword boundary and move an even number of words.

6)Configure a DMA channel to move data from CRSRCx to a destination in the DSP memory. The channel transfers should be triggered by the CrEVTx. The size of the transfers should be set to VCTHRLD1/8 for 8-bit mode, VCTHRLD1/4 for 10-bit mode, or VCTHRLD1/6 for dense 10-bit mode. (This is because 4, 2, or 3 pixels are packed per FIFO word, the DMA is moving 32-bit words from CRSRCx to the memory, and there are half the number of pixels in the Cr FIFO as in the Y FIFO.) The DMA must start on a double-word boundary and move an even number of words.

7)Write to the video port interrupt enable register (VPIE) to enable overrun (COVRx) and capture complete (CCMPx) interrupts, if desired.

3-44

Video Capture Port

SPRU629

Page 105 Page 107
Page 106
Image 106
Texas Instruments TMS320C64x DSP manual Capturing Video in BT.656 or Y/C Mode
Page 105 Page 107

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.