Manuals / Texas Instruments / Computer Equipment / Network Card

Texas Instruments TMS320C64x DSP manual F1C, F2C, and Frmc status bits, in VCBSTAT, are not

Models: TMS320C64x DSP

1 306
Download 306 pages 13.79 Kb
Page 131
Image 131

Video Capture Registers

Table 3–23. Video Capture Channel B Control Register (VCBCTL)

Field Descriptions (Continued)

 

 

 

 

 

 

Description

 

 

Bit

field†

symval†

Value

BT.656 or Y/C Mode

 

Raw Data Mode

 

TSI Mode

30

BLKCAP

 

 

Block capture events bit. BLKCAP functions as a capture FIFO

 

 

 

 

reset without affecting the current programmable register values.

 

 

 

 

The F1C, F2C, and FRMC status bits, in VCBSTAT, are not

 

 

 

 

updated. Field or frame complete interrupts and vertical interrupts

 

 

 

 

are also not generated.

 

 

 

 

 

 

 

 

Clearing BLKCAP does not enable DMA events during the field

 

 

 

 

where the bit is cleared. Whenever BLKCAP is set and then

 

 

 

 

cleared, the software needs to clear the field and frame status

 

 

 

 

bits (F1C, F2C, and FRMC) as part of the BLKCAP clear

 

 

 

 

operation.

 

 

 

 

 

 

CLEAR

0

Enables DMA events in the video frame that follows the video

 

 

 

 

frame where the bit is cleared. (The capture logic must sync to

 

 

 

 

the start of the next frame after BLKCAP is cleared.)

 

 

BLOCK

1

Blocks DMA events and flushes the capture channel FIFOs.

 

 

 

 

 

29–21

Reserved

–

0

Reserved. The reserved bit location is always read as 0. A value

 

 

 

 

written to this field has no effect.

 

 

 

 

 

 

 

 

 

 

 

20

FINV

 

 

Detected field invert bit.

 

 

 

 

 

 

FIELD1

0

Detected 0 is field 1.

 

Not used.

 

Not used.

 

 

 

 

 

 

FIELD2

1

Detected 0 is field 2.

 

Not used.

 

Not used.

 

 

 

 

 

 

 

 

 

19–18

Reserved

–

0

Reserved. The reserved bit location is always read as 0. A value

 

 

 

 

written to this field has no effect.

 

 

 

 

 

 

 

 

 

17

VRST

 

 

VCOUNT reset method bit.

 

 

 

 

V1EAV

0

Start of vertical blank

 

Not used.

 

Not used.

 

 

 

 

 

 

 

 

(1st V = 1 EAV or

 

 

 

 

 

 

 

 

VCTL2 active edge)

 

 

 

 

 

 

V0EAV

1

End of vertical blank

 

Not used.

 

Not used.

 

 

 

 

(1st V = 0 EAV or

 

 

 

 

 

 

 

 

VCTL2 inactive edge)

 

 

 

 

 

 

 

 

 

 

 

 

 

† For CSL implementation, use the notation VP_VCBCTL_field_symval

‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.

SPRU629

Video Capture Port

3-69

Page 130 Page 132
Page 131
Image 131
Texas Instruments TMS320C64x DSP manual F1C, F2C, and Frmc status bits, in VCBSTAT, are not
Page 130 Page 132

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.