Raw Data Capture Mode

3.7 Raw Data Capture Mode

In the raw data capture mode, the data is sampled by the interface only when the CAPEN signal is active. Data is captured at the rate of the sender’s clock, without any interpretation or start/stop of capture based on the data values.

To ensure initial capture synchronization to the beginning of a frame, an optional setup synchronization enable (SSE) bit is provided in VCxSTRT1. If the SSE bit is set, then when the VCEN bit is set to 1, the video port will not start capturing data until after detecting two vertical blanking intervals. If the SSE bit is cleared to 0, capture begins immediately when the VCEN bit is set.

The incoming digital video capture data is stored in the FIFO, which is 2560-bytes (in dual-channel operation) or 5120-bytes deep (in single-channel operation). The memory-mapped location YSRCx is associated with the Y buffer. The YSRCx location is a read-only register and is used to access video data samples stored in the buffer.

The captured data set size is set by VCxSTOPn. The VCXSTOP and VCYSTOP bits set the 24-bits of data set size (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits). Capture is complete and the appropriate F1C, F2C, or FRMC bit is set when the captured data size reaches the combined VCYSTOP and VCXSTOP value.

The video port generates a YEVT after the specified number of new samples has been captured in the buffer. The number of samples required to generate YEVTx is programmable and is set in the VCTHRLDn bits of VCxTHRLD. On every YEVT, the DMA should move data from the buffer to the DSP memory. When moving data from the buffer to the DSP memory, the DMA should use the YSRCx location as a source address.

3.7.1Raw Data Capture Notification

Raw data mode captures a single data packet of information using only CAPEN for control. Field information is available only for channel A operation using the FID input on VCTL3. If the RDFE bit in VCACTL is set, then the video port samples the FID input at the start of each data block (when DCOUNT = 0 and CAPENA is active) to determine the current field. In this case, the CON, FRAME, CF1, and CF2 bits in VCxCTL are used in a manner identical to BT.656 mode (see section 3.4.1).

For channel B operation or when the RDFE bit in VCACTL is not set, no field information is available. Some flexibility in capture and DSP notification is still provided in order to accommodate various DMA structures and processing flows. Each raw data packet is treated similar to a progressive scan video frame. The raw data mode uses the CON and FRAME bits of VCxCTL in a slightly different manner, as listed in Table 3–11.

3-32

Video Capture Port

SPRU629

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Texas Instruments TMS320C64x DSP manual Raw Data Capture Mode, Raw Data Capture Notification
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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