Raw Data Capture Mode

 

Table 3–11. Raw Data Mode Capture Operation

 

 

 

 

 

 

 

VCxCTL Bit

 

 

 

 

 

 

 

 

 

CON

FRAME

CF2

CF1

Operation

 

 

 

 

 

 

 

0

0

x

x

Noncontinuous frame capture. FRMC is set after data block capture

 

 

 

 

 

and causes CCMPx to be set. Capture will halt upon completion of the

 

 

 

 

 

next frame unless the FRMC bit is cleared. (DSP has the entire next

 

 

 

 

 

frame time to clear FRMC.)

 

0

1

x

x

Single frame capture. FRMC is set after data block capture and causes

 

 

 

 

 

CCMPx to be set. Capture is halted until the FRMC bit is cleared.

 

1

0

x

x

Continuous frame capture. FRMC is set after data block capture and

 

 

 

 

 

causes CCMPx to be set (CCMPx interrupt can be disabled). The port

 

 

 

 

 

will continue capturing frames regardless of the state of FRMC.

 

1

1

x

x

Reserved

 

 

 

 

 

 

 

The CON bit controls the capture of multiple frames. When CON = 1, continuous capture is enabled, the video port captures incoming frames (assuming the VCEN bit is set) without the need for DSP interaction. It relies on a DMA structure with circular buffering capability to service the capture FIFO. When CON = 0, continuous capture is disabled, the video port sets the frame capture complete bit (FRMC) in VCxSTAT upon the capture of each frame. Once the capture complete bit is set, at most, one more frame can be received before capture operation is halted (as determined by the FRAME bit state). This prevents subsequent data from overwriting previous frames until the DSP has a chance to update DMA pointers or process those frames.

3.7.2Raw Data FIFO Packing

Captured data is always packed into 64-bits before being written into the capture FIFO(s). The packing and byte ordering is dependant upon the capture data size and the device endian mode. For little-endian operation (default), data is packed into the FIFO from right to left; for big-endian opera- tion, data is packed from left to right.

SPRU629

Video Capture Port

3-33

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Texas Instruments TMS320C64x DSP manual Raw Data Mode Capture Operation, Raw Data Fifo Packing
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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