Operational Details

Any time a packet with a PCR is received, the timestamp for that packet is compared with the PCR value in software. A PLL is implemented in software to synchronize the STCLK with the system time clock. The DSP updates the VIC input register (VICIN) using the output from this algorithm, which in turn drives the VCTL output that controls the system time clock VCXO.

If f is the frequency of PCRs in the incoming bit stream, the interpolation rate R of the VCTL output is given in Equation 6–1, where k is determined by the precision β specified by you.

Equation 6–1. Relationship Between Interpolation Rate and Input Frequency

R + kf

Equation 6–2 gives the relation between k and the precision β .

Equation 6–2. Relationship of Frequency Multiplier to Precision

k u ￿3 ( (p2(2b * 1)2)￿3)

Table 6–2 gives some k and R values for different β ’s with f fixed at 40 kHz. Once a suitable interpolation frequency is determined, the clock divider can be set.

Table 6–2. Example Values for Interpolation Rate

β

k

R

 

 

 

9

96.0

3.8 MHz

10

151.0

6.0 MHz

11

240.0

9.6 MHz

12

381.0

15.2 MHz

13

605.0

24.2 MHz

14

960.0

38.4 MHz

15

1523.0

60.9 MHz

16

2418.0

96.7 MHz

 

 

 

6-4

VCXO Interpolated Control Port

SPRU629

Page 271
Image 271
Texas Instruments TMS320C64x DSP manual Example Values for Interpolation Rate

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.