Fpcount

Video Display Mode Selection

The image line counter (ILCOUNT) and the image pixel counter (IPCOUNT) track the visible image within the field. ILCOUNT begins counting at the first display image line in each field. IPCOUNT begins counting at the first dis- played image pixel on each line. They stop counting when they reach the image height and image width as specified in the video display field n image size register (VDIMGSZn).

The video clock counter (VCCOUNT) counts VCLKIN transitions to determine when to increment FPCOUNT and IPCOUNT as determined by the video display mode. In Y/C mode, FPCOUNT and IPCOUNT increment on each VCLKIN rising edge. In BT.656 mode, FPCOUNT and IPCOUNT increment on every other VCLKIN rising edge. In raw mode, FPCOUNT and IPCOUNT increment on every 1 to 16 VCLKIN cycles as programmed by the INCPIX bits in the video display threshold register (VDTHRLD).

FPCOUNT and FLCOUNT are compared to various values to determine when to assert and negate various control signals. The 12-bit FPCOUNT is used to determine where to enable and disable horizontal sync and blanking informa- tion along each scan line. The state of FPCOUNT is reflected in the VDXPOS bits of the video display status register (VDSTAT). Figure 4–5 shows how the horizontal blanking and horizontal synchronization signals are triggered. (HBLNK and HSYNC are shown active high).

Figure 4–5. Horizontal Blanking and Horizontal Sync Timing

FPCOUNT	718	719	720	735	736	799	800	857	0	1
FPCOUNT
HBLNK

HSYNC

FPCOUNT = HBLNKSTART

FPCOUNT = HBLNKSTOP

FPCOUNT = HSYNCSTOP

FPCOUNT = HSYNCSTART

The 12-bit FLCOUNT counts which scan line is being generated. The FLCOUNT is reset to 1 after reaching the count specified in VDFRMSZ. (For BT.656 operation, the FRMHIGHT would be set to 525 (525/60 operation) or 625 (625/50 operation).) The state of FLCOUNT is reflected in the VDYPOS bits of VDSTAT. Figure 4–6 shows how the vertical blanking, vertical synchro- nization, and field identification signals are triggered. (VBLNK and VSYNC are shown active high.)

4-6

Video Display Port

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual Horizontal Blanking and Horizontal Sync Timing, Fpcount

Models: TMS320C64x DSP

Figure 4–5. Horizontal Blanking and Horizontal Sync Timing

TMS320C64x DSP specifications