VSYNCYSTOP2, VSYNCXSTOP2 | Texas Instruments TMS320C64x DSP specification

Video Display Registers

4.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)

The video display field 2 vertical synchronization end register (VDVSYNE2) controls the end of vertical synchronization in field 2. The VDVSYNE2 is shown in Figure 4–58 and described in Table 4–25.

Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.The VSYNC signal is deasserted whenever the frame line counter (FLCOUNT) is equal to VSYNCYSTOP2 and the frame pixel counter (FPCOUNT) is equal to VSYNCXSTOP2.

Figure 4–58. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)

31	28	27	16
	Reserved		VSYNCYSTOP2

	R-0		R/W-0
15	12	11	0

	Reserved		VSYNCXSTOP2

	R-0		R/W-0

Legend: R = Read only; R/W = Read/Write; -n= value after reset

Table 4–25. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Field Descriptions

Bit	field†	symval†	Value	Description
31–28	Reserved	–	0	Reserved. The reserved bit location is always read as
				0. A value written to this field has no effect.

27–16	VSYNCYSTOP2	OF(value)	0–FFFh	Specifies the line where VSYNC is deasserted for
				field 2.

15–12	Reserved	–	0	Reserved. The reserved bit location is always read as
				0. A value written to this field has no effect.

11–0	VSYNCXSTOP2	OF(value)	0–FFFh	Specifies the pixel where VSYNC is deasserted in
				field 2.

† For CSL implementation, use the notation VP_VDVSYNE2_field_symval

4-82

Video Display Port

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

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In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual VSYNCYSTOP2, VSYNCXSTOP2

Models: TMS320C64x DSP

Figure 4–58. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)

VSYNCYSTOP2

VSYNCXSTOP2

Bit

field†

Value

OF(value)

OF(value)

TMS320C64x DSP specifications