Y’b’ = (–1Ya+ 17Yb + 17Yc – 1Yd) /32

Video Output Filtering

Examples of luma edge and chroma edge replication for 2⋅ interspersed to co-sited output are shown in Figure 4–23 and Figure 4–24, respectively.

Figure 4–23. Luma Edge Replication

a

a

b

c

x

y

z

z

y

Horizontal Image Size

a a’

b b’

c

Leading edge

 

 

replicated luma

 

 

Y’a = Ya

Y’b = Yb

Y’c = Yc

Y’a’ = (–1Ya+ 17Ya + 17Yb – 1Yc) /32

x

x’ y

y’ z z’

Trailing edge

 

 

 

replicated luma

Y’x = Yx

Y’y= Yy

Y’z = Yz

 

Y’z’ = (–1Yy+ 17Yz + 17Yz – 1Yy) /32

Y’y’ = (–1Yx+ 17Yy + 17Yz – 1Yz ) /32

Y’x’ = (–1Yw+ 17Yx + 17Yy – 1Yz ) /32

Figure 4–24. Interspersed Chroma Edge Replication

 

cd

 

ab

 

 

a

ab

b

 

c

cd

d

w

wx

x

y

yz

z

 

 

 

yz

wx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Leading edge

 

 

 

 

 

 

 

 

 

 

Horizontal Image Size

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Trailing edge

 

 

 

a

a’

b

b’

c

c’

d

w

w’

x x’

y

y’

z

 

z’

 

 

 

 

replicated chroma

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

replicated chroma

 

 

 

samples

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

samples

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cb’a = (–3Cbcd+ 33Cbab + 101Cbab –3Cbcd

)/128

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cb’z = (–3Cbwx+ 101Cbyz + 33Cbyz –3Cbwz)/128

Cr’a = (–3Crcd+ 33Crab + 101Crab –3Crcd)/128

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cr’z = (–3Crwx+ 101Cryz + 33Cryz –3Cbwx)/128

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cb’b = (–3Cbab+ 101Cbab + 33Cbcd –3Cbef)/128

 

 

 

 

 

 

 

 

 

 

Cb’y = (–3Cbuv+ 33Cbwx + 101Cbyz –3Cbyz)/128

 

Cr’b = (–3Crab+ 101Crab + 33Crcd –3Cref)/128

 

 

 

 

 

 

 

 

 

 

Cr’y = (–3Cruv+ 33Crwx + 101Cryz –3Cbyz)/128

 

 

 

 

 

 

 

 

 

 

 

Cb’

c

= (–3Cb

ab

+ 33Cb

ab

+ 101Cb

cd

–3Cb

)/128

 

 

 

 

Cb’x = (–3Cbuv+ 101Cbwx + 33Cbyz –3Cbyz)/128

 

 

 

 

 

 

 

 

ef

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cr’c = (–3Crab+ 33Crab + 101Crcd –3Cref)/128

 

 

 

 

Cr’

x

= (–3Cr

uv

+ 101Cr

wx

+ 33Cr

yz

–3Cr

yz

)/128

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cb’d = (–3Cbab+ 101Cbcd + 33Cbef –3Cbgh)/128

Cb’w = (–3Cbst+ 33Cbuv + 101Cbwx –3Cbyz)/128

 

 

 

 

 

Cr’d = (–3Crab+ 101Crcd + 33Cref –3Crgh)/128

Cr’w = (–3Crst+ 33Cruv + 101Crwx –3Cryz)/128

 

 

 

4-24

Video Display Port

SPRU629

Page 168 Page 170
Page 169
Image 169
Texas Instruments TMS320C64x DSP manual Luma Edge Replication
Page 168 Page 170

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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