Intel 815 manual 16.2.5

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

						R
		16.2.5.	ISR—Interrupt Status Register		326
		16.2.6.	Error Identity, Mask and Status Registers		327
			16.2.6.1. Page Table Error handling in Intel® 815 Chipset		327
			16.2.6.2. Resetting the Page Table Error		328
			16.2.6.3.	EIR—Error Identity Register	329
			16.2.6.4.	EMR—Error Mask Register	329
			16.2.6.5.	ESR—Error Status Register	330
	16.3.	Display Interface Control			331
		16.3.1.	FW_BLC—FIFO Watermark and Burst Length Control		331
17.	LCD / TV-Out Register Description				333
	17.1.	HTOTAL—Horizontal Total Register			333
	17.2.	HBLANK—Horizontal Blank Register			334
	17.3.	HSYNC—Horizontal Sync Register			335
	17.4.	VTOTAL—Vertical Total Register			336
	17.5.	VBLANK—Vertical Blank Register			337
	17.6.	VSYNC—Vertical Sync Register			338
	17.7.	LCDTV_C—LCD/TV-Out Control Register			339
	17.8.	OVRACT—Overlay Active Register			342
	17.9. BCLRPAT— Border Color Pattern Register				342
18.	Local Memory Interface				343
	18.1.	DRT—DRAM Row Type			343
	18.2.	DRAMCL—DRAM Control Low			344
	18.3.	DRAMCH—DRAM Control High			345
19.	I/O Control Registers				347
	19.1.	HVSYNC—HSYNC/VSYNC Control Register			347
	19.2.	GPIO Registers			348
		19.2.1.	GPIOAGeneral Purpose I/O Control Register A		348
		19.2.2.	GPIOBGeneral Purpose I/O Control Register B		350
20.	Display And Cursor Registers				353
	20.1. DISP_SL—Display Scan Line Count				353
	20.2. DISP_SLC—Display Scan Line Count Range Compare				354
	20.3.	Pixel Pipeline Control			355
		20.3.1.	PIXCONF—Pixel Pipeline Configuration		355
		20.3.2.	BLTCNTL—BLT Control		357
		20.3.3.	SWF[1:3]—Software Flag Registers		357
		20.3.4.	DPLYBASE—Display Base Address Register		358
		20.3.5.	DPLYSTAS—Display Status Select Register		359
	20.4.	Hardware Cursor			361
		20.4.1.	CURCNTR—Cursor Control Register		361
		20.4.2.	CURBASE—Cursor Base Address Register		362
		20.4.3.	CURPOS—Cursor Position Register		362
21.	Appendix A: Mode Parameters				363

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