Intel 815 manual FP Vesa VGA Mode, FP / 740 Data Ordering, Fpvsync Control, Fphsync Control

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

Bit		Description
28	FP VESA VGA Mode
	0	= Disable. Use the LCD / TV Timing Generator. VGA Sync Polarity is ignored. FP Sync Polarity is
		used. Centering can be enabled for fixed resolution flat panels or TVs. The Flat Panel Dot clock
		PLL timing registers must be used for both flat panels and TVs. After these registers are written the
		Lock Dot Clock PLL N/M Registers must be set to 1 which makes the Dot Clock PLL only use the
		Flat Panel PLL registers.
	1	= Enable. Use the VGA Timing Generator. VGA Sync polarity is passed though and FP Sync Polarity
		is ignored. Centering must be disabled. Also set bit 0 of this register, Lock Dot Clock PLL N/M
		Regs to a 0 which allows normal programming of the Dot Clock PLL registers. This bit should be
		disabled when driving a TV.
27:17	Reserved. MBZ
16:15	Reserved.
14	FP / 740 Data Ordering
	0	= 740 Compliant Data Ordering:
	1	= Flat Panel Data Ordering: R[7:0] ‘ G[7:4] followed by G[3:0] ‘ B[7:0].
13	LCD Information Data Enable. When enabled, transfers data from GC to the external device during
	Vertical sync. This transfer should be qualified by blank signal.
	0	= Disable
	1	= Enable. (Currently planned for Debug purposes)
12	Reserved.
11	FPVSYNC Control.
	1	= FPVSYNC is disabled.
		•If in FP VESA VGA Mode, then this pin goes to the level of the VGA VSYNC when disabled.
		•If not in FP VESA VGA Mode, then this pin goes is in the deasserted state as specified by the
		VSYNC Polarity Control field.
	0	= FPVSYNC is enabled.
		•When in FP VESA VGA Mode, then the VGA timing generator is the source of this signal
		•When not in FP VESA VGA Mode, then the source of this signal is this timing generator.
10	FPHSYNC Control.
	1	= FPHSYNC is disabled.
		•If in FP VESA VGA Mode, then this pin goes to the level of the VGA HSYNC when disabled.
		•If not in FP VESA VGA Mode, then this pin goes is in the deasserted state as specified by the
		HSYNC Polarity Control field.
	0	= FPHSYNC is enabled.
		•When in FP VESA VGA Mode, then the VGA timing generator is the source of this signal
		•When not in FP VESA VGA Mode, then the source of this signal is this timing generator.
9	FPVSYNC Output Control.
	1	= Tristates the FPVSYNC pin.
	0	= FPVSYNC is active unless LCD / TV Out Enable is deasserted.
	Though this bit is provided, the GC always use VSYNC as output.

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