Intel 815 manual 31. CR32Extended Vertical Sync Start Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

9.6.31.CR32Extended Vertical Sync Start Register

I/O (and Memory Offset) Address:				3B5h/3D5h (index=32h)
Default:				00h
Attributes:				Read/Write
7				4	3	0
			Reserved (0000)		Vertical Sync Start Bits 11:8
		Bit			Description
	7:4		Reserved. Read as 0s. This field must be 0s when this register is written.
	3:0		Vertical Sync Start Bits [11:8]. The vertical sync start is a 10-bit or 12-bit value that specifies the
			beginning of the vertical sync pulse relative to the beginning of the active display area.
			In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical sync start
			is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the
			Vertical Sync Start Register (CR10), and the 2 most significant bits are supplied by bits 7 and 2 of the
			Overflow Register (CR07). In standard VGA modes, these 4 bits of this register are not used.
			In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical display end is
			specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the
			Vertical Sync Start Register (CR10), and the 4 most significant bits are supplied by these 4 bits of this
			register.
			This 10-bit or 12-bit value should be programmed to be equal to the number of scan lines from the
			beginning of the active display area to the start of the vertical sync pulse. Since the active display area
			always starts on the 0th scan line, this number should be equal to the number of the scan line on which
			the vertical sync pulse begins.

134