Intel 815 manual 35. CR40Extended Start Address Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.6.35.CR40Extended Start Address Register

I/O (and Memory Offset) Address:				3B5h/3D5h (index=40h)
Default:				00h
Attributes:				Read/Write
7		6	5	0
	Start Addr	Reserved		Start Address Bits 23:18
	Enable	(0)
	Bit			Description

7Extended Mode Start Address Enable. This bit is used only in extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, to signal the graphics controller to update the start address. In extended modes, the start address is specified with a 30 bit value. These 30 bits, which are provided by the Start Address Low Register (CR0D), the Start Address High Register (CR0C), the Extended Start Address High Register (CR42) and bits [5:0] of this register, are double-buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance. To change the start address in extended modes, all three registers must be set for the new value, and then this bit of this register must be set to 1. Only if this is done, will the graphics controller update the start address on the next VSYNC. When this update has been performed, the graphics controller will set bit 7 of this register back to 0.

6Reserved. Read as 0s. This field must be 0s when this register is written.

5:0	Start Address Bits [23:18]. This start address is a 16 bit value that specifies the memory address offset
	from the beginning of the frame buffer, or a 32 bit buffer address at which the data to be shown in the active
	display area begins. (default is 0)
	In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the start address is
	specified with a 16-bit value. The eight bits of the Start Address High Register (CR0C) provide the eight
	most significant bits of this value, while the eight bits of the Start Address Low Register (CR0D) provide
	the eight least significant bits.
	In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the start address is
	specified with a 32-bit value. Bits 31:24 of this value are provided by the Extended Start Address High
	Register (CR42). Bits 23:18 of this value are provided by bits 5:0 of this register. Bits 17:10 of this value
	are provided by the Start Address High Register (CR0C). Bits 9:2 of this value are provided by the Start
	Address Low Register (CR0D). Bits 1:0 of this value are always 0, and therefore not provided. Note that,
	in extended modes, these 32 bits from these four registers are double-buffered and synchronized to
	VSYNC to ensure that changes occurring on the screen as a result of changes in the start address
	always have a smooth or instantaneous appearance. To change the start address in extended modes,
	all four registers must be set for the new value, and then bit 7 of this register must be set to 1. Only if
	this is done, will the graphics controller update the start address on the next VSYNC. When this update
	has been performed, the graphics controller will set bit 7 of this register back to 0.

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