Intel 815 manual HORZPH-Horizontal Phase Register 279 15.4.3.4

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

		15.4.3.3.		HORZ_PH—Horizontal Phase Register	279
		15.4.3.4.		INIT_PH—Initial Phase Register	280
		15.4.4.	Overlay Destination Window Position/Size Registers		281
		15.4.4.1.		DWINPOS—Destination Window Position Register	281
		15.4.4.2.		DWINSZ—Destination Window Size Register	281
		15.4.5.	Overlay Source Size Registers		282
		15.4.5.1.		SWID—Source Width Register	282
		15.4.5.2.		SWIDQW—Source Width In QWords Register	283
		15.4.5.3.		SHEIGHT—Source Height Register	284
		15.4.6.	Overlay Scale Factor Registers		285
		15.4.6.1.		YRGBSCALE—Y/RGB Scale Factor Register	285
		15.4.6.2.		UVSCALE—UV Scale Factor Register	286
		15.4.7.	Overlay Color Correction Registers		287
		15.4.7.1.		OV0CLRC0—Overlay 0 Color Correction 0 Register	287
		15.4.7.2.		OV0CLRC1—Overlay 0 Color Correction 1 Register	287
		15.4.8.	Overlay Destination Color Key Registers		288
		15.4.8.1.		DCLRKV—Destination Color Key Value Register	288
		15.4.8.2.		DCLRKM—Destination Color Key Mask Register	289
		15.4.9.	Overlay Source Color Key Registers		290
		15.4.9.1.		SCLRKVH—Source Color Key Value High Register	290
		15.4.9.2.		SCLRKVL—Source Color Key Value Low Register	291
		15.4.9.3.		SCLRKM—Source Color Key Mask Register	291
		15.4.10.	Overlay Configuration Registers		293
		15.4.10.1. OV0CONF—Overlay Configuration Register			293
		15.4.11.	OV0CMD—Overlay Command Register		294
		15.4.12.	Overlay Alpha Blend Window Position/Size Registers		298
		15.4.12.1. AWINPOS—Alpha Blend Window Position Register			298
		15.4.12.2. AWINSZ—Alpha Blend Window Size Register			299
	15.5.	Overlay Flip Instruction			299
16.	Instruction, Memory, and Interrupt Control Registers				301
	16.1.	Instruction Control Registers			301
		16.1.1.	FENCE—Graphics Memory Fence Table Registers		301
		16.1.2.	PGTBL_CTL—Page Table Control Register		303
		16.1.3.	PGTBL_ER—Page Table Error Register		304
		16.1.4.	PGTBL_ERRMSK—Page Table Error Mask Register		306
		16.1.5.	RINGBUF—Ring Buffer Registers		308
		16.1.6.	HWS_PGA—Hardware Status Page Address Register		310
		16.1.7.	IPEIR—Instruction Parser Error Identification Register (debug)		311
		16.1.8.	IPEHR—Instruction Parser Error Header Register (debug)		311
		16.1.9.	INSTDONE—Instruction Stream Interface Done Register		312
		16.1.10.	NOPID—NOP Identification Register		313
		16.1.11.	INSTPM—Instruction Parser Mode Register		314
		16.1.12.	INSTPS—Instruction Parser State Register (debug)		315
		16.1.13.	BBP_PTR—Batch Buffer Parser Pointer Register (debug)		317
		16.1.14.	ABB_STR—Active Batch Buffer Start Address Register (debug)		317
		16.1.15.	ABB_END—Active Batch Buffer End Address Register (debug)		318
		16.1.16.	DMA_FADD—DMA Engine Fetch Address (debug)		318
		16.1.17.	MEM_MODE—Memory Interface Mode Register (debug)		319
	16.2.	Interrupt Control Registers			320
		16.2.1.	HWSTAM—Hardware Status Mask Register		322
		16.2.2.	IER—Interrupt Enable Register		323
		16.2.3.	IIR—Interrupt Identity Register		324
		16.2.4.	IMR—Interrupt Mask Register		325

9