Intel 815 manual 12.3.9. BR08-Destination X1

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

12.3.9.BR08—Destination X1 and X2

Memory Offset Address:	40020h
Default:	None
Attributes:	RO; DWord accessible

BR08 is loaded by either PIXEL_BLT, SCANLINE_BLT, or TEXT_BLT instructions. The PIXEL_BLT instruction only writes the destination X coordinate register.

31	28	27	16
Reserved. Must be Zero			Destination X2 coordinate (right) [11:00]
15	12	11	0
Reserved. Must be Zero			Destination X1 or X coordinate (left) [11:00]
Bit			Descriptions
31:28	Reserved. Must be Zero.
27:16	Destination X2 coordinate. These 12 bits specify the right most X coordinate which is written to the
	destination if not clipped. The comparison is inclusive with a less than or equal. The byte address of
	this coordinate is:
	scan line address + X2 * bytes/pixel.
15:12	Reserved. Must be Zero.
11:0	Destination X1 or X coordinate (left). These 12 bits specify the left most X coordinate which is
	written to the destination. This is also the working register, where it changes while the BLT Engine is
	working. The comparison is inclusive with a greater than or equal. The byte address of this coordinate
	is:
	scan line address + X1 * bytes/pixel.
	Note:
	Some instructions affect only one pixel (requiring only one coordinate); other instructions affect
	multiple pixels and need both coordinates.

192