Intel 815 manual 12.3.8. BR07-Setup Color Pattern Address

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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12.3.8.BR07—Setup Color Pattern Address

Memory Offset Address:					4001Ch
Default:					None
Attributes:					RO; DWord accessible
31				26	25		16
			Reserved. Must be Zero		Setup Color Pattern Address Bits [25:16]
15					6	5	0
				Setup Color Pattern Address Bits [15:6]			Reserved. Must be Zero
		Bit			Descriptions
	31:26			Reserved. Must be Zero. The maximum GC graphics address is 64 MBs.
	25:6			Pattern Address. These 20 bits specify the starting address of the color pattern from the SETUP_BLT
				instruction. This register works identically to the Pattern Address register, but this version is only used
				with the SCANLINE_BLT instruction execution.
				The pattern data must be located on a pattern-size boundary. The pattern is always of 8x8 pixels, and
				therefore, its size is dependent upon its pixel depth. The pixel depth may be 8, 16, or 24 bits per pixel
				if the pattern is in color (the pixel depth of a color pattern must match the pixel depth to which the
				graphics system has been set). Monochrome patterns require 8 bytes and is supplied through the
				instruction. Color patterns of 8, 16, and 24 bits per pixel color depth must start on 64-byte, 128-byte
				and 256-byte boundaries, respectively.
				Note:
				In the case of 24 bits per pixel, each scan line’s worth (each row of 8 pixels) of pattern data takes up
				24 consecutive bytes.
	5:0			Reserved. Must be Zero. These bits always return 0 when read.

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