Intel 815 manual Gfxcmdparserbatchbuffer, Instruction Target 30h

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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11.2.17. GFXCMDPARSER_BATCH_BUFFER

The GFXCMDPARSER_BATCH_BUFFER instruction is used to inform the input interface to parse an instruction buffer. The address on the instruction buffers is in graphics memory that should translate to a physical address in main memory. Note that in case of an AGP device batch buffers can be in AGP memory only.

The batch buffer instruction packet implements a protection ID. The protection ID is recorded as protection state by the parser when it starts a Batch buffer instruction executed from one of the rings. Chained Batch buffer instructions cannot change the protection state of the parser. If a batch buffer is pushed into the stack at a chain point, this state has to be stored as well. The protection state modifies the parser behavior as follows:

•In Unprotected Mode the parser generates an error if it parses a store DWORD immediate instruction. It is assumed that an unprotected batch buffer has not been verified by the driver and can have invalid store DWORD immediate instructions that write over protected areas in cacheable memory.

•In protected state the parser will allow all instructions to be parsed. It is assumed that a batch buffer identified as protected has been verified by the driver to ensure that store DWORD immediate instructions do not corrupt the operating system.

The Intel® 815 chipset hardware implementation has batch buffer size limit set at 512 KB - 8B.

The instruction needs a Buffer Start Address and a Buffer End Address that both must be QW aligned physical memory addresses. Using this start and end address, the batch buffer size definition is:

Batch Buffer Size = Buffer End Address - Buffer Start Address + 8 Bytes

This means the batch buffer does include valid commands up to and including the end address location.

@Start_Address			Valid Command \
@Start_Address + 8			Valid Command \
... ...			> Total Size = End - Start + 8B
@End_Address - 8 Valid Command / must be limited to 512KB-8B
@End_Address			Valid Command /
	DWord	Bits	Description
	0	31:29	Client: 000 – Instruction Parser
		28:23	Instruction Target: 30h
		22:6	Reserved.
		5:0	Dword Length: 01h
	1	31:3	Buffer Start Address: Must be a QW aligned physical memory address.
		2:1	Reserved.
		0	Protection id: 1 = Un-Protected, 0 = Protected
	2	31:3	Buffer End Address: Must be a QW aligned physical memory address.
		2:0	Reserved. MBZ

Helpful Hint: Use GFXCMDPARSER_NOP_IDENTIFICATION to pad buffer to a QW length.

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