Intel 815 manual Figures

Models: 815

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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

Figures

Figure 1.

Intelâ 815 Chipset System Block Diagram

18

Figure 2.

Intel® 82815 Chipset GMCH Block Diagram

19

Figure 3.

Conceptual Platform PCI Configuration Diagram

23

Figure 4.

Device Mode Auto-Detect Flowchart

25

Figure 5.

System Memory Address Map

29

Figure 6.

Detailed Memory System Address Map

29

Figure 7.

Graphics Controller Register Memory and I/O Map

30

Figure 8.

GTT Mapping

42

Figure 9.

Source Corruption in BLT with Overlapping Source and Destination Locations 54

Figure 10.

Correctly Performed BLT with Overlapping Source and Destination Locations. 55

Figure 11.

Suggested Starting Points for Possible Source & Destination Overlap

 

 

Situations

56

Figure 12.

Representation of On-Screen Single 6-Pixel Line in the Frame Buffer

57

Figure 13.

Representation of On-Screen 6x4 Array of Pixels in the Frame Buffer

58

Figure 14.

Pattern Data -- Always an 8x8 Array of Pixels

60

Figure 15.

8bpp Pattern Data -- Occupies 64 Bytes (8 quadwords)

61

Figure 16.

16bpp Pattern Data -- Occupies 128 Bytes (16 quadwords)

61

Figure 17.

24bpp Pattern Data -- Occupies 256 Bytes (32 quadwords)

61

Figure 18.

2bpp Pattern Data -- Occupies 256 Bytes (32 quadwords)

62

Figure 19.

On-Screen Destination for Example Pattern Fill BLT

63

Figure 20.

Pattern Data for Example Pattern Fill BLT

64

Figure 21.

Results of Example Pattern Fill BLT

65

Figure 22.

On-Screen Destination for Example Character Drawing BLT

66

Figure 23.

Source Data in System Memory for Example Character Drawing BLT

66

Figure 24.

Results of Example Character Drawing BLT

68

Figure 25

Display Fields and Dimensions CRxx Control Registers

110

Figure 26.

Graphics Controller Instruction Interface

143

Figure 27.

Ring Buffers

144

Figure 28.

Batch Buffer Sequence

146

Figure 29.

Instruction Format For First DWord

150

Figure 30.

Rectangle Vertices

205

Figure 31.

State Variable Relationships

214

Figure 32.

State Variable Relationships

215

Figure 33.

State Variable Relationships

217

Figure 34

Mip-map Surface Organization Example

218

Figure 35.

State Variable Relationships

222

Figure 36.

State Variable Relationships

224

Figure 37.

State Variable Relationships

225

Figure 38.

State Variable Relationships

226

Figure 39.

State Variable Relationships

227

Figure 40.

State Variable Relationships

230

Figure 41.

Gamma Correction Unit Block Diagram

271

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Intel 815 manual Figures